Memory apparatus supporting multiple width configurations
First Claim
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1. A memory apparatus comprising:
- an input to receive width selection information;
an interface to exchange data with a remote device;
a plurality of memory subsections, each subsection including columns of memory cells coupled to corresponding sense amplifiers; and
routing coupling the memory subsections with the interface, the routing supporting first and second width configurations responsive to the width selection information;
whereinin the first width configuration, the routing conveys data of a first data width between a first integer number of the memory subsections and the interface, and the plurality of memory subsections collectively provide a first memory depth, andin the second width configuration, the routing conveys data of a second data width between a second integer number of the memory subsections and the interface, and the plurality of memory subsections collectively provide a second memory depth;
wherein the memory apparatus loads the sense amplifiers in the first number of the memory subsections for read operations in the first width configuration and loads the sense amplifiers in the second number of memory subsections for read operations in the second width configuration.
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Abstract
Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.
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Citations
20 Claims
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1. A memory apparatus comprising:
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an input to receive width selection information; an interface to exchange data with a remote device; a plurality of memory subsections, each subsection including columns of memory cells coupled to corresponding sense amplifiers; and routing coupling the memory subsections with the interface, the routing supporting first and second width configurations responsive to the width selection information; wherein in the first width configuration, the routing conveys data of a first data width between a first integer number of the memory subsections and the interface, and the plurality of memory subsections collectively provide a first memory depth, and in the second width configuration, the routing conveys data of a second data width between a second integer number of the memory subsections and the interface, and the plurality of memory subsections collectively provide a second memory depth; wherein the memory apparatus loads the sense amplifiers in the first number of the memory subsections for read operations in the first width configuration and loads the sense amplifiers in the second number of memory subsections for read operations in the second width configuration. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A memory controller, comprising:
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an output to send width selection information to at least one variable-width memory; a data interface having a width N for exchanging data with the at least one variable-width memory in a point-to-point configuration; wherein when the controller exchanges data with only a first variable-width memory, the width selection information comprises a memory width of N; and when the controller exchanges data with the first variable-width memory and a second variable-width memory, the width selection information comprises a memory width of N/2. - View Dependent Claims (18, 19, 20)
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Specification