Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements

• US 8,412,915 B2
• Filed: 11/30/2001
• Issued: 04/02/2013
• Est. Priority Date: 11/30/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Master, Paul L., Smith, Stephen J., Watson, John
• Primary Examiner(s): VICARY, KEITH E
• Application Number:
  US09/997,530
• Publication Number:
  US 20030102889A1
• Time in Patent Office: 4,141 Days
• Field of Search: 712/15, 712/35, 712/36, 712/29
• US Class Current: 712/15
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes.

Claims

1. A system for adaptive configuration, the system comprising:

a memory adapted to store configuration information including a first configuration information and a second configuration information;

a first computational unit having a configurable basic architecture including a first plurality of heterogeneous computational elements and a first interconnection network configurably coupling the first plurality of heterogeneous computational elements together, the first interconnection network configuring interconnections between the first plurality of heterogeneous computational elements in response to the first configuration information to perform a basic computational function; and

a second computational unit having a configurable complex processing architecture including a second plurality of heterogeneous computational elements and a second interconnection network configurably coupling the second plurality of heterogeneous computational elements together, the second interconnection network configuring interconnections between the second plurality of heterogeneous computational elements in response to the second configuration information to perform a complex processing function.

2. The system of claim 1, wherein the configuration information provides a first system operating mode of the plurality of operating modes.

3. The system of claim 1, wherein the first plurality of heterogeneous computational elements are configured to generate a request for the second configuration information.

4. The system of claim 1, wherein the memory comprises a third plurality of heterogeneous computational elements configured to perform a memory function in response to the configuration information.

5. The system of claim 1, wherein the configuration information is transferred to the system from a machine-readable medium or through a wireless interface.

6. The system of claim 1, wherein the configuration information is embodied as a plurality of discrete information data packets or as a stream of information data bits.

7. The system of claim 1, wherein the system is embodied within an integrated circuit.

8. The system of claim 1, wherein the computational units are organized in a configurable computing matrix and the computing matrix is coupled to a matrix interconnection network.

9. The system of claim 8, wherein the matrix interconnection network is coupled to a plurality of configurable computing matrices, each configurable computing matrix having a plurality of computational units.

10. The system of claim 9, wherein a first configured function of the configurable computing matrix is as a controller, and wherein the controller function includes sending configuration information via the matrix interconnection network to configure one of the plurality of configurable computing matrices.

11. The system of claim 8, wherein a first configured function of the configurable computing matrix is as a controller.

12. The system of claim 11, wherein the controller is a RISC controller.

13. The system of claim 1, wherein the first interconnection network operates as a Boolean interconnection network and a data interconnection network, the first interconnection network further allowing the transmission of data and configuration information.

14. The system of claim 13, wherein the matrix interconnection network transmits configuration information to the computing matrix to configure the computing matrix to perform the functions.

15. The system of claim 1, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

16. The system of claim 15, wherein the first computational unit operates at a bit level;

and

wherein the second computational unit operates at a word level.

17. The system of claim 16, wherein the basic computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

18. The system of claim 1, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

19. The system of claim 18, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

20. The system of claim 1, wherein the first plurality of heterogeneous computational elements includes a function generator and an adder, a register and an adder, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the second plurality of heterogeneous computational elements includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

21. The system of claim 20, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

22. The system of claim 21, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

23. The system of claim 1, wherein the basic computational function includes one of a group of linear operation, memory, memory management, and bit level manipulation;

and

wherein the complex processing function is one of a group of fixed point arithmetic functions, floating point arithmetic functions, filter functions, and transformation functions.

24. The system of claim 23, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

25. The system of claim 24, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

26. The system of claim 25, wherein the basic computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

27. The system of claim 26, wherein the second plurality of heterogeneous computational elements each perform a function from the group of multiplication, addition, subtraction, accumulation, summation, byte passing, and dynamic shift.

28. The system of claim 1, further comprising a third interconnection network coupled to the first computational unit and the second computational unit, the third interconnection network sending the configuration information to the computational units.

29. The system of claim 28, wherein the first interconnection network has denser interconnections than the interconnections of the third interconnection network.

30. The system of claim 1, wherein the first interconnection network includes multiplexers coupled to the first plurality of heterogeneous computational elements, and the second interconnection network includes other multiplexers coupled to the second plurality of heterogeneous computational elements.

31. The system of claim 30, wherein the configuration information includes control signals to control the multiplexers.

32. A system for adaptive configuration, the system comprising:

a memory adapted to store configuration information including a first configuration information and a second configuration information;

a first configurable basic computational logic unit including a first plurality of heterogeneous computational elements and a first interconnection network for forming a first configurable architecture, the first interconnection network configurably coupling the first plurality of heterogeneous computational elements together;

the first interconnection network configuring interconnections between the first plurality of heterogeneous computational elements in response to the first configuration information to perform a basic computational function; and

a second configurable complex processing unit including a second plurality of heterogeneous computational elements and a second interconnection network for forming a second configurable architecture, the second interconnection network configurably coupling the second plurality of heterogeneous computational elements together;

the second interconnection network configuring interconnections between the second plurality of heterogeneous computational elements in response to the second configuration information to perform a complex processing function.

33. The system of claim 32, wherein the configuration information provides a first system operating mode of the plurality of operating modes.

34. The system of claim 32, wherein the first plurality of heterogeneous computational elements are configured to generate a request for the second configuration information.

35. The system of claim 32, wherein the memory comprises a third plurality of heterogeneous computational elements configured to perform a memory function in response to the configuration information.

36. The system of claim 32, wherein the configuration information is transferred to the system from a machine-readable medium or through a wireless interface.

37. The system of claim 32, wherein the configuration information is embodied as a plurality of discrete information data packets or as a stream of information data bits.

38. The system of claim 32, wherein the system is embodied within an integrated circuit.

39. The system of claim 32, wherein the logic unit and processing unit are organized in a configurable computing matrix and the configurable computing matrix is coupled to a matrix interconnection network.

40. The system of claim 39, wherein the matrix interconnection network is coupled to a plurality of configurable computing matrices, each configurable computing matrix having a plurality of logic and processing units.

41. The system of claim 40, wherein a first configured function of the configurable computing matrix is as a controller, and wherein the controller function includes sending configuration information via the matrix interconnection network to configure one of the plurality of configurable computing matrices.

42. The system of claim 39, wherein a first configured function of the configurable computing matrix is as a controller.

43. The system of claim 42, wherein the controller is a RISC controller.

44. The system of claim 32, wherein the first plurality of heterogeneous computational elements are organized as a basic computational architecture;

and

wherein the second plurality of heterogeneous computational elements are organized as a complex processing architecture.

45. The system of claim 32, wherein the first interconnection network operates as a Boolean interconnection network and a data interconnection network, the first interconnection network further allowing the transmission of data and configuration information.

46. The system of claim 45, wherein the matrix interconnection network transmits configuration information to the computing matrix to configure the computing matrix to perform the functions.

47. The system of claim 32, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

48. The system of claim 47, wherein the first configurable basic computational logic unit operates at a bit level;

and

wherein the second configurable complex processing unit operates at a word level.

49. The system of claim 48, wherein the basic computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

50. The system of claim 32, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

51. The system of claim 50, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

52. The system of claim 32, wherein the first plurality of heterogeneous computational elements includes a function generator and an adder, a register and an adder, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the second plurality of heterogeneous computational elements includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

53. The system of claim 52, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

54. The system of claim 53, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

55. The system of claim 32, wherein the basic computational function includes one of a group of linear operation, memory, memory management, and bit level manipulation;

and

wherein the complex processing function is one of a group of fixed point arithmetic functions, floating point arithmetic functions, filter functions, and transformation functions.

56. The system of claim 55, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

57. The system of claim 56, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

58. The system of claim 57, wherein the basic computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

59. The system of claim 58, wherein the second plurality of heterogeneous computational elements each perform a function from the group of multiplication, addition, subtraction, accumulation, summation, byte passing, and dynamic shift.

60. The system of claim 32, further comprising a third interconnection network coupled to the first configurable basic computational unit and the second configurable complex processing unit, the third interconnection network sending the configuration information to the units.

61. The system of claim 60, wherein the first interconnection network has denser interconnections than the interconnections of the third interconnection network.

62. The system of claim 32, wherein the first interconnection network includes multiplexers coupled to the first plurality of heterogeneous computational elements, and the second interconnection network includes other multiplexers coupled to the second plurality of heterogeneous computational elements.

63. The system of claim 62, wherein the configuration information includes control signals to control the multiplexers.

64. The system of claim 32, wherein the first interconnection network provides a third configuration information to reconfigure the first configurable basic computational unit to perform a second computational function, the memory being adapted to store the third configuration information.

65. A method for adaptive configuration of an integrated circuit, the method comprising:

receiving configuration information;

storing the configuration information in a memory; and

in response to the configuration information;

configuring interconnections between a first plurality of heterogeneous computational elements of the integrated circuit via a first interconnection network of the integrated circuit to provide a configurable basic computational unit to perform a basic computational function, the first interconnection network configurably coupling the first plurality of heterogeneous computational elements together; and

configuring interconnections between the second plurality of heterogeneous computational elements of the integrated circuit via the second interconnection network of the integrated circuit to provide a configurable complex computational unit to perform a complex processing function, the second interconnection network configurably coupling the second plurality of heterogeneous computational elements together.

66. The method of claim 65, further comprising requesting authorization to receive the configuration information.

67. The method of claim 65, wherein the configuration information provides a first system operating mode of the plurality of operating modes.

68. The method of claim 65, wherein the configuration information is received from a machine-readable medium or via a wireless interface.

69. The method of claim 65, wherein the computational units are organized in a configurable computing matrix and the configurable computing matrix is coupled to a matrix interconnection network.

70. The method of claim 69, wherein the matrix interconnection network is coupled to a plurality of configurable computing matrices, each configurable computing matrix having a plurality of computational units.

71. The method of claim 70, wherein a first configured function of the configurable computing matrix is as a controller, and wherein the controller function includes sending configuration information via the matrix interconnection network to configure one of the plurality of configurable computing matrices.

72. The method of claim 69, wherein a first configured function of the configurable computing matrix is as a controller.

73. The method of claim 72, wherein the controller is a RISC controller.

74. The method of claim 69, wherein the matrix interconnection network transmits configuration information to the computing matrix to configure the computing matrix to perform the functions.

75. The method of claim 65, wherein the first plurality of heterogeneous computational elements are organized as a basic computational architecture;

and

wherein the second plurality of heterogeneous computational elements are organized as a complex processing architecture.

76. The method of claim 65, wherein the first interconnection network operates as a Boolean interconnection network and a data interconnection network, the first interconnection network further allowing the transmission of data and configuration information.

77. The method of claim 65, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

78. The method of claim 77, wherein the configurable basic computational logic unit operates at a bit level;

and

wherein the configurable complex processing unit operates at a word level.

79. The method of claim 78, wherein the basic computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

80. The method of claim 65, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

81. The method of claim 80, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

82. The method of claim 65, wherein the first plurality of heterogeneous computational elements includes a function generator and an adder, a register and an adder, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the second plurality of heterogeneous computational elements includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

83. The method of claim 82, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

84. The method of claim 83, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

85. The method of claim 65, wherein the basic computational function includes one of a group of linear operation, memory, memory management, and bit level manipulation;

and

wherein the complex processing function is one of a group of fixed point arithmetic functions, floating point arithmetic functions, filter functions, and transformation functions.

86. The method of claim 85, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

87. The method of claim 86, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

88. The method of claim 87, wherein the basic computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

89. The method of claim 88, wherein the second plurality of heterogeneous computational elements each perform a function from the group of multiplication, addition, subtraction, accumulation, summation, byte passing, and dynamic shift.

90. The method of claim 65, further comprising a third interconnection network coupled to the configurable basic computational unit and the configurable complex computational unit, the third interconnection network sending the configuration information to the units.

91. The method of claim 90, wherein the first interconnection network has denser interconnections than the interconnections of the third interconnection network.

92. The method of claim 65, wherein the first interconnection network includes multiplexers coupled to the first plurality of heterogeneous computational elements, and the second interconnection network includes other multiplexers coupled to the second plurality of heterogeneous computational elements.

93. The method of claim 92, wherein the configuration information includes control signals to control the multiplexers.

94. The method of claim 65, wherein the first interconnection network provides a third configuration information to reconfigure the configurable basic computational unit to perform a second computational function, the memory being adapted to store the third configuration information.

95. A method for adaptive configuration of an integrated circuit, the integrated circuit having a first plurality of heterogeneous computational elements, a second plurality of heterogeneous computational elements, and an interconnection network coupled to the memory, the interconnection network having and a second interconnection network configurably coupling the second plurality of heterogeneous computational elements together, the method comprising:

transmitting configuration information;

wherein the configuration information is received;

storing the received configuration information in a memory; and

in response to the configuration information;

configuring interconnections between a first plurality of heterogeneous computational elements via a first interconnection network to provide a configurable basic computational unit to perform a basic computational function, the first interconnection network configurably coupling the first plurality of heterogeneous computational elements together; and

configuring interconnections between a second plurality of heterogeneous computational elements via a second interconnection network to provide a configurable complex computational unit to perform a complex processing function, the second interconnection network configurably coupling the second plurality of heterogeneous computational elements together.

96. The method of claim 95, further comprising requesting authorization to receive the configuration information.

97. The method of claim 95, wherein the configuration information provides a first system operating mode of the plurality of operating modes.

98. The method of claim 95, wherein the configuration information is received from a machine-readable medium or via a wireless interface.

99. The method of claim 95, wherein the computational units are organized in a configurable computing matrix and the configurable computing matrix is coupled to a matrix interconnection network.

100. The method of claim 99, wherein the matrix interconnection network is coupled to a plurality of configurable computing matrices, each configurable computing matrix having a plurality of computational units.

101. The method of claim 100, wherein a first configured function of the configurable computing matrix is as a controller, and wherein the controller function includes sending configuration information via the matrix interconnection network to configure one of the plurality of configurable computing matrices.

102. The method of claim 99, wherein a first configured function of the configurable computing matrix is as a controller.

103. The method of claim 102, wherein the controller is a RISC controller.

104. The method of claim 95, wherein the first plurality of heterogeneous computational elements are organized as a basic computational architecture;

and

wherein the second plurality of heterogeneous computational elements are organized as a complex processing architecture.

105. The method of claim 95, wherein the first interconnection network operates as a Boolean interconnection network and a data interconnection network, the first interconnection network further allowing the transmission of data and configuration information.

106. The method of claim 105, wherein the matrix interconnection network transmits configuration information to the computing matrix to configure the computing matrix to perform the functions.

107. The method of claim 95, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

108. The method of claim 107, wherein the configurable basic computational logic unit operates at a bit level;

and

wherein the configurable complex processing unit operates at a word level.

109. The method of claim 108, wherein the basic computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

110. The method of claim 95, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

111. The method of claim 110, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

112. The method of claim 95, wherein the first plurality of heterogeneous computational elements includes a function generator and an adder, a register and an adder, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the second plurality of heterogeneous computational elements includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

113. The method of claim 112, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

114. The method of claim 113, wherein the basic computational function comprises bit level manipulation;

and

wherein the complex processing function comprises word level manipulation.

115. The method of claim 95, wherein the basic computational function includes one of a group of linear operation, memory, memory management, and bit level manipulation;

and

wherein the complex processing function is one of a group of fixed point arithmetic functions, floating point arithmetic functions, filter functions, and transformation functions.

116. The method of claim 115, wherein the basic computational function is a logic function;

and

wherein the complex processing function is a digital signal processing function.

117. The method of claim 116, wherein the basic computational function comprises it level manipulation;

and

wherein the complex processing function comprises word level manipulation.

118. The method of claim 116, wherein the basic computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

119. The method of claim 118, wherein the second plurality of heterogeneous computational elements each perform a function from the group of multiplication, addition, subtraction, accumulation, summation, byte passing, and dynamic shift.

120. The method of claim 95, further comprising a third interconnection network coupled to the configurable basic computational unit and the configurable complex computational unit, the third interconnection network sending the configuration information to the units.

121. The method of claim 120, wherein the first interconnection network has denser interconnections than the interconnections of the third interconnection network.

122. The method of claim 95, wherein the first interconnection network includes multiplexers coupled to the first plurality of heterogeneous computational elements, and the second interconnection network includes other multiplexers coupled to the second plurality of heterogeneous computational elements.

123. The method of claim 122, wherein the configuration information includes control signals to control the multiplexers.

124. The method of claim 95, wherein the first interconnection network provides a third configuration information to reconfigure the configurable basic computational unit to perform a second computational function, the memory being adapted to store the third configuration information.