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Optimizing power usage by factoring processor architectural events to PMU

  • US 8,412,970 B2
  • Filed: 12/19/2011
  • Issued: 04/02/2013
  • Est. Priority Date: 12/29/2006
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a plurality of cores;

    a plurality of shared caches coupled to the plurality of cores;

    logic circuitry to detect whether one of a plurality of architectural events has occurred within one of the plurality of cores, wherein each architectural event is to be monitored based on a programmed channel;

    a plurality of thermal sensors of a first core to provide thermal data for the first core;

    a plurality of counters of the first core each to count a number of occurrences of one of the architectural events;

    a bus to couple the plurality of counters and the plurality of thermal sensors; and

    a power control unit to cause a power sequence in response to occurrence of one of the architectural events, wherein the power control unit is to determine whether to modify a power state of one of the plurality of cores based on the occurrence.

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