Execution monitor for electronic design automation

• US 8,413,103 B2
• Filed: 04/15/2009
• Issued: 04/02/2013
• Est. Priority Date: 03/13/2009
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Potemski, Andrew Stanley, Tyson, John Scott, Eustes, Steven Robert
• Primary Examiner(s): Do, Thuan
• Application Number:
  US12/423,955
• Publication Number:
  US 20100235795A1
• Time in Patent Office: 1,448 Days
• Field of Search: 716/139, 716/100, 716/101, 716/102, 716106-113, 716/134, 703/22
• US Class Current: 716/139
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Embodiments of a computer system, a method, a graphical user interface and a computer-program product (i.e., software) for use with the computer system are described. A chip designer may use these devices and techniques to configure and monitor the execution of tasks in a user-configurable electronic-design-automation (EDA) flow associated with a circuit or chip design. In particular, using an intuitive and interactive graphical user interface in EDA software, the chip designer can configure and initiate execution of the EDA flow. Then, during execution of EDA tasks in the EDA flow, an execution monitor in the graphical user interface may provide a graphical representation of real-time execution status information for the EDA tasks. Moreover, using the EDA software, the chip designer can debug the circuit or chip design if any errors or problems occur.

Claims

1. A method for monitoring execution of a user-configurable electronic design automation (EDA) flow, comprising:

providing first signals to display an EDA flow-control environment on a display, wherein the flow-control environment includes an execution-monitoring window;

initiating, based on a first user input, the user-configurable EDA flow, which is displayed as a top-level sequence of blocks, wherein a block in the sequence of blocks comprises a user-configurable collection of sub-block flows, wherein a sub-block in a sub-block flow represents a sequence of EDA tasks that are performed on the circuit design;

receiving, from the user, modifications to one or more blocks or sub-blocks at any level of a hierarchy of blocks and sub-blocks;

monitoring execution of the user-configurable EDA flow tasks, wherein the EDA flow tasks result in a realization of an integrated chip design product idea, and wherein the EDA flow tasks comprise logic design, functional verification, synthesis, top-level routing, and timing analysis; and

displaying, based on a second user input, execution status information and progress in execution of the blocks and the sub-blocks at a desired level of the hierarchy of blocks and associated sub-blocks, wherein the displayed execution status information and progress in execution reflects the received modifications from the user.

2. The method of claim 1, further comprising receiving the second user input to debug an error that has occurred during execution of the user configurable EDA flow, and receiving a third user input to view detailed information on the error that occurred.

3. The method of claim 2, further comprising:

receiving fourth user input to stop execution of the user-configurable EDA flow prior to the debugging; and

receiving fifth user input to resume execution of the user-configurable EDA flow after the debugging.

4. The method of claim 1, wherein execution of the user-configurable EDA flow includes monitoring the execution of the sequence of EDA tasks;

and

wherein the execution status information includes execution status of the sequence of EDA tasks.

5. The method of claim 4, wherein at least some of the sequence of EDA tasks are predefined.

6. The method of claim 1, wherein the execution status information includes color-coded information.

7. The method of claim 1, wherein at least portions of the sequence of blocks are predefined.

8. The method of claim 1, further comprising providing third signals to display a graphical representation in the sequence of blocks in the flow-control environment.

9. The method of claim 8, wherein the graphical representation of the sequence of blocks is presented in a what-you-see-is-what-you-get format.

10. The method of claim 8, wherein the sequence of blocks is defined by drag-and-drop assembly of blocks.

11. The method of claim 8, wherein arrow icons between flows in the graphical representation indicate sources and destinations of information during the user-configurable EDA flow.

12. The method of claim 8, wherein progress and any errors during execution of the user-configurable EDA flow are indicated in the graphical representation using color-coded information.

13. The method of claim 1, wherein the sequence of blocks includes blocks that are executed in parallel.

14. A computer-program product for use in conjunction with a computer system, the computer-program product comprising a non-transitory computer-readable storage medium and a computer-program mechanism embedded therein for configuring the computer system to monitor execution of a user-configurable electronic design automation (EDA) flow, comprising:

instructions for providing first signals to display an EDA flow-control environment on a display, wherein the flow-control environment includes an execution-monitoring window;

instructions for initiating, based on a first user input, the user-configurable EDA flow, which is displayed as a top-level sequence of blocks, wherein a block in the sequence of blocks comprises a user-configurable collection of sub-block flows, wherein a sub-block in a sub-block flow represents a sequence of EDA tasks that are performed on the circuit design;

instructions for receiving, from the user, modifications to one or more blocks or sub-blocks at any level of a hierarchy of blocks and sub-blocks;

instructions for monitoring execution of the user-configurable EDA flow tasks, wherein the EDA flow tasks result in a realization of an integrated chip design product idea, and wherein the EDA flow tasks comprise logic design, functional verification, synthesis, top-level routing, and timing analysis; and

instructions for displaying, based on a second user input, execution status information and progress in execution of the blocks and the sub-blocks at a desired level of the hierarchy of blocks and associated sub-blocks, wherein the displayed execution status information and progress in execution reflects the received modifications from the user.

15. The computer-program product of claim 14, further comprising instructions for receiving the second user input to debug an error that has occurred during execution of the user configurable EDA flow, and receiving a third user input to view detailed information on the error that occurred.

16. The computer-program product of claim 15, further comprising:

receiving fourth user input to stop execution of the user-configurable EDA flow prior to the debugging; and

receiving fifth user input to resume execution of the user-configurable EDA flow after the debugging.

17. The computer-program product of claim 14, wherein the execution status information includes color-coded information.

18. The computer-program product of claim 14, further comprising providing third signals to display a graphical representation in the sequence of blocks in the flow-control environment.

19. The computer-program product of claim 18, wherein arrow icons between flows in the graphical representation indicate sources and destinations of information during the user-configurable EDA flow.

20. The computer-program product of claim 18, wherein progress and any errors during execution of the user-configurable EDA flow are indicated in the graphical representation using color-coded information.

21. The computer-program product of claim 14, wherein the sequence of blocks includes blocks that are executed in parallel.

22. A computer system, comprising:

a processor;

memory;

a program module, wherein the program module is stored in the memory and configured to be executed by the processor to monitor execution of a user-configurable electronic design automation (EDA) flow, the program module including;

instructions for providing first signals to display an EDA flow-control environment on a display, wherein the flow-control environment includes an execution-monitoring window;

instructions for initiating, based on a first user input, the user-configurable EDA flow, which is displayed as a top-level sequence of blocks, wherein a block in the sequence of blocks comprises a user-configurable collection of sub-block flows, wherein a sub-block in a sub-block flow represents a sequence of EDA tasks that are performed on the circuit design;

instructions for receiving, from the user, modifications to one or more blocks or sub-blocks at any level of a hierarchy of blocks and sub-blocks;

instructions for monitoring execution of the user-configurable EDA flow tasks, wherein the EDA flow tasks result in a realization of an integrated chip design product idea, and wherein the EDA flow tasks comprise logic design, functional verification, synthesis, top-level routing, and timing analysis; and

instructions for displaying, based on a second user input, execution status information and progress in execution of the blocks and the sub-blocks at a desired level of the hierarchy of blocks and associated sub-blocks, wherein the displayed execution status information and progress in execution reflects the received modifications from the use.

23. A non-transitory computer-readable storage medium storing instructions for a graphical user interface on a computer, the instructions comprising:

instructions for displaying the graphical user interface in a flow-control environment, wherein the graphical user interface is configured to monitor execution of a user-configurable electronic design automation (EDA) flow comprising a top-level sequence of blocks, wherein the user-configurable EDA flow comprises a user-configurable collection of sub-block flows, wherein a sub-block in a sub-block flow represents a sequence of EDA tasks that result in a realization of an integrated chip design product idea, and wherein the EDA flow tasks comprise logic design, functional verification, synthesis, top-level routing, and timing analysis; and

instructions for displaying an execution-monitoring window in the graphical user interface, wherein the execution-monitoring window is configured to display a graphical representation of a sequence of blocks in the user-configurable EDA flow and, based at least in part on monitoring of execution of the user-configurable EDA flow, and to display graphical execution status information and progress during execution of the user-configurable EDA flow, wherein the displayed execution status information and progress in execution reflects modifications received from the user to one or more blocks or sub-blocks at any level of a hierarchy of blocks and sub-blocks.