One-transistor pixel array

• US 8,415,176 B2
• Filed: 06/30/2011
• Issued: 04/09/2013
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US13/174,207
• Publication Number:
  US 20120056248A1
• Time in Patent Office: 649 Days
• Field of Search: 438/14, 438/17, 438/49
• US Class Current: 438/14
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column.

Claims

1. A method for operating an array of chemically-sensitive field-effect transistors (chemFETs), at least some chemFETs in the array of chemFETs comprising a first source/drain terminal and a second source/drain terminal, and a floating gate coupled to a passivation layer, the method comprising:

selecting a chemFET in the array of chemFETs, the selected chemFET having a first source/drain terminal directly connected to a selected first line in a plurality of first lines, and having a second first source/drain terminal directly connected to a selected second line in a plurality of second lines, wherein each first line in the plurality of first lines is directly connected to the first source/drain terminals of a corresponding first plurality of chemFETs in the array of chemFETs, and each second line in the plurality of second lines is directly connected to the second source/drain terminals of a corresponding second plurality of chemFETs in the array of chemFETs;

applying a read voltage on the selected first line to induce current flow between the selected first line and the selected second line through the selected chemFET during a read interval, thereby establishing an output voltage level on the selected second line; and

reading the selected chemFET based on the output voltage level on the selected second line.

2. The method of claim 1, wherein the output voltage level on the selected second line is established based on a threshold voltage of the selected chemFET.

3. The method of claim 1, wherein the output voltage level indicates an ion-concentration of an analyte solution coupled to the floating gate of the selected chemFET via the passivation layer.

4. The method of claim 1, further comprising pre-charging the selected second line to a pre-charge voltage level prior to the read interval.

5. The method of claim 1, further comprising compensating for leakage current through unselected chemFETs connected to the selected second line during the read interval.

6. The method of claim 1, wherein the compensating for leakage current comprises coupling a current sink to the selected second line during the read interval.

7. The method of claim 1, wherein applying the read voltage boosts by capacitive coupling the floating gate of the selected chemFET to a boosted voltage level, thereby inducing the current flow to establish the output voltage level on the selected second line.

8. The method of claim 7, further comprising applying a voltage to corresponding first lines connected to unselected chemFETs connected to the selected second line, thereby biasing by capacitive coupling the floating gates of the unselected chemFETs to an inhibit voltage level.

9. The method of claim 8, wherein a magnitude voltage difference between the boosted voltage level and the inhibit voltage level is at least 200 mV.

10. The method of claim 1, wherein reading the selected chemFET comprises holding an analog value of the output voltage level on the selected second line during read interval, converting the analog value to a digital value, and reading the selected chemFET based on the digital value.

11. The method of claim 1, wherein reading the selected chemFET comprises directly converting the output voltage level on the selected second line to a digital value, and reading the selected chemFET based on the digital value.

12. The method of claim 1, wherein the chemFETs in the array are arranged in rows and columns, each first line is directly connected to the first source/drain terminals of chemFETs arranged in a corresponding column in the plurality of columns, and each second conductive line is directly connected to the second source/drain terminals of chemFETs arranged in a corresponding row in the plurality of rows.