Two-transistor pixel array

• US 8,415,177 B2
• Filed: 06/30/2011
• Issued: 04/09/2013
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith, Johnson, Kim, Milgrew, Mark
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US13/174,222
• Publication Number:
  US 20120001237A1
• Time in Patent Office: 649 Days
• Field of Search: 438/14, 438/17, 438/49
• US Class Current: 438/14
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

A two-transistor (2T) pixel comprises a chemically-sensitive transistor (ChemFET) and a selection device which is a non-chemically sensitive transistor. A plurality of the 2T pixels may form an array, having a number of rows and a number of columns. The ChemFET can be configured in a source follower or common source readout mode. Both the ChemFET and the non-chemically sensitive transistor can be NMOS or PMOS device.

Claims

1. A method for operating an array of pixels, at least some pixels in the array comprising a chemically-sensitive field-effect transistor (chemFET) including a first source/drain terminal and a second source/drain terminal, and a floating gate coupled to a passivation layer, and further comprising a select transistor including a first source/drain terminal, a second source/drain terminal, and a gate terminal, wherein the first source/drain terminal of the second transistor is directly connected to the first source/drain terminal of the chemFET, the method comprising:

selecting a pixel in the array of pixels, wherein the second source/drain terminal of the chemFET of the selected pixel is directly connected to a first line, and the second source/drain terminal of the select transistor of the selected pixel is directly connected to a second line;

applying a bias voltage to one of the first and second lines;

applying a pass voltage to the gate terminal of the select transistor of the selected pixel during a read interval, thereby inducing current flow between the first line and the second line through the selected pixel to establish an output voltage level on the other of the first and second lines; and

reading the selected pixel based on the output voltage level on the other of the first and second lines.

2. The method of claim 1, wherein the output voltage level on the other of the first and second lines is based on a threshold voltage of the chemFET of the selected pixel.

3. The method of claim 1, wherein the output voltage level on the other of the first and second lines indicates an ion-concentration of an analyte solution coupled to the floating gate of the selected chemFET via the passivation layer.

4. The method of claim 1, wherein a plurality of pairs of lines are coupled to pixels in the array, and each pair of lines includes a given first line directly connected to second source/drain terminals of chemFETs of a corresponding first plurality of pixels in the array, and includes a given second line directly connected to second source/drain terminals of second transistors of the corresponding first plurality of pixels in the array.

5. The method of claim 4, wherein:

a plurality of third lines are coupled to pixels in the array, each third line coupled to gate terminals of second transistors of a corresponding second plurality of pixels; and

applying the pass voltage to the gate terminal of the select transistor of the selected pixel comprises applying the pass voltage to a third line coupled to the gate terminal of the select transistor of the selected pixel.

6. The method of claim 1, further comprising providing a bias current to the selected pixel via the other of the first and second lines.

7. The method of claim 1, further comprising pre-charging the other of the first and second lines to a pre-charge voltage level prior to the read interval.

8. The method of claim 1, wherein channels of the chemFET and the select transistor of pixels in the array have different conductivity types.

9. A method for operating an array of pixels arranged in a plurality of rows and a plurality of columns, at least some pixels in the array comprising a chemically-sensitive field-effect transistor (chemFET) including a first source/drain terminal and a second source/drain terminal, and a floating gate coupled to a passivation layer, and further comprising a select transistor including a first source/drain terminal, a second source/drain terminal, and a gate terminal, wherein the first source/drain terminal of the second transistor is directly connected to the first source/drain terminal of the chemFET, the method comprising:

selecting a pair of adjacent pixels arranged in a given column in the plurality of columns, wherein the second source/drain terminal of the select transistor of a first pixel of the selected pair is directly connected to a first column line, the second source/drain terminal of the select transistor of a second pixel of the selected pair is directly connected to a second column line, and the second source/drain terminals of the chemFETs of the selected pair are directly connected to a third column line;

applying a bias voltage to the third column line;

applying pass voltages to the gate terminals of the select transistors of the first and second pixels of the selected pair during a read interval, thereby inducing current flow between the first column line and the third column line through the first pixel of the selected pair to establish an output voltage level on the first column line, and inducing current flow between the second column line and the third column line through the second pixel of the selected pair to establish an output voltage level on the second column line; and

reading the first pixel of the selected pair based on the output voltage level on the first column line, and reading the second pixel of the selected pair based on the output voltage level on the second column line.

10. The method of claim 9, wherein the output voltage levels on the first and second column lines are based on threshold voltages of the chemFETs of the first and second pixels of the selected pair respectively.

11. The method of claim 9, wherein the output voltage levels on the first and second column lines indicate ion-concentrations of analyte solutions coupled to the floating gates of the first and second pixels of the selected pair respectively.

12. The method of claim 9, wherein:

a plurality of row lines are coupled to pixels in the array of pixels, a given row line in the plurality of pixels directly connected to control gate terminals of select transistors of pixels arranged in a corresponding row in the plurality of rows; and

applying pass voltages to the gate terminals of the select transistors of the first and second pixels of the selected pair comprises applying the pass voltages to row lines coupled to the gate terminals of the select transistors of the first and second pixels of the selected pair.

13. The method of claim 9, further comprising pre-charging the first and second column lines to pre-charge voltage levels prior to the read interval.

14. The method of claim 9, wherein channels of the chemFET and the select transistor of each of the pixels in the array have the same conductivity type.

15. The method of claim 14, wherein the channels of the chemFET and the select transistor of each of the pixels in the array are formed in a continuous doped region.

16. The method of claim 9, wherein the second column line is directly connected to a second source/drain terminal of a select transistor of another pixel arranged in the given column, and said another pixel is next to the second pixel of the selected pair.

17. The method of claim 9, wherein a plurality of sets of column lines are coupled to pixels in the array, wherein a particular set in the plurality of sets is coupled to a corresponding pair of adjacent pixels arranged in a particular column in the plurality of columns, the particular set including a particular first column line directly connected to the second source/drain terminal of the select transistor of a first pixel of the corresponding pair, a particular second column line directly connected to the second source/drain terminal of the select transistor of a second pixel of the corresponding pair, and a particular third column line directly connected to the second source/drain terminals of the chemFETs of the corresponding pair.