Three dimensional integration and methods of through silicon via creation

• US 8,415,238 B2
• Filed: 01/14/2010
• Issued: 04/09/2013
• Est. Priority Date: 01/14/2010
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Farooq, Mukta G., Kinser, Emily R., Wise, Richard, Yusuff, Hakeem
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): CHOI, CALVIN Y
• Application Number:
  US12/687,282
• Publication Number:
  US 20110171827A1
• Time in Patent Office: 1,181 Days
• Field of Search: 438/514, 438/524, 438/525, 438/533, 438/618, 438/620, 438/622, 438/627, 438/628, 438/638, 438/639, 438/643, 438/644, 438652-655, 257/E21.575, 257E21584-E21586
• US Class Current: 438/525
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.

Claims

1. A method comprising:

patterning a photoresist layer on a structure to define an opening and expose a first planar area on a first substrate layer, wherein the first substrate layer is a silicon layer;

etching the exposed first planar area to form a cavity having a first depth in the structure;

removing a portion of the photoresist to expose a second planar area on the substrate layer;

implanting ions in an exposed portion of the second planar area to define an exposed doped portion of the first substrate layer and an exposed undoped portion of the first substrate layer;

etching to remove the exposed doped portion of the first substrate layer; and

etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.

2. The method of claim 1, wherein the structure includes a first wafer and a second wafer.

3. The method of claim 1, wherein the structure includes a first chip and a second chip.

4. The method of claim 1, wherein the structure has a substrate portion and a wiring level portion, and the substrate includes a silicon material.