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Front to back resistive random access memory cells

  • US 8,415,650 B2
  • Filed: 07/01/2010
  • Issued: 04/09/2013
  • Est. Priority Date: 07/02/2009
  • Status: Active Grant
First Claim
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1. A resistive random access memory cell formed on a semiconductor substrate comprising:

  • first and second diffused regions disposed in the semiconductor substrate;

    a polysilicon gate layer disposed above, insulated from, and self aligned with inner edges of the first and second diffused regions;

    a region of a first metal interconnect layer disposed above and insulated from the semiconductor substrate;

    a first contact electrically connecting the first diffused region with the region of the first metal interconnect layer;

    a first via electrically connected to and extending upward from the region of the first metal interconnect layer;

    a second via electrically connected to and extending upward from the region of the first metal interconnect layer;

    a first resistive random access memory device including a first barrier metal layer formed over and in electrical contact with the first via, a dielectric layer formed over the first barrier metal layer, an ion source layer formed over the dielectric layer, a second barrier metal layer formed over and in electrical contact with the ion source layer, and a first portion of a second metal interconnect layer formed over and in electrical contact with the second barrier metal layer; and

    a second resistive random access memory device including a first barrier metal layer formed over and in electrical contact with the second via, an ion source layer formed over the first barrier metal layer, a dielectric layer formed over the ion source layer, a second barrier metal layer formed over and in electrical contact with the ion source layer, and a second portion of the second metal interconnect layer formed over and in electrical contact with the second barrier metal layer.

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