Front to back resistive random access memory cells

• US 8,415,650 B2
• Filed: 07/01/2010
• Issued: 04/09/2013
• Est. Priority Date: 07/02/2009
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Greene, Jonathan, Hawley, Frank W., McCollum, John
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US12/829,311
• Publication Number:
  US 20110001108A1
• Time in Patent Office: 1,013 Days
• Field of Search: 257 2- 5, 257/E45.002
• US Class Current: 257/2
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/882 Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8845 Carbon or carbides
• CPC Class Codes: Y10S 438/90 Bulk effect device making

Abstract

A resistive random access memory cell is formed on a semiconductor substrate. First and second diffused regions are disposed in the semiconductor substrate. A polysilicon gate is disposed above the first and second diffused regions. A first contact connects the first diffused region with a region of a first metal layer. A first interlayer dielectric layer is formed over the first metal layer and includes first and second vias, each including conductive plugs connected to the region of the first metal layer. First and second resistive random access memory devices formed over the first interlayer dielectric layer have first and second terminals, and include a dielectric layer and an ion source layer. The first terminals of the first and second resistive random access memory devices are coupled to the first metal layer by the first and second conductive plugs.

Claims

1. A resistive random access memory cell formed on a semiconductor substrate comprising:

first and second diffused regions disposed in the semiconductor substrate;

a polysilicon gate layer disposed above, insulated from, and self aligned with inner edges of the first and second diffused regions;

a region of a first metal interconnect layer disposed above and insulated from the semiconductor substrate;

a first contact electrically connecting the first diffused region with the region of the first metal interconnect layer;

a first via electrically connected to and extending upward from the region of the first metal interconnect layer;

a second via electrically connected to and extending upward from the region of the first metal interconnect layer;

a first resistive random access memory device including a first barrier metal layer formed over and in electrical contact with the first via, a dielectric layer formed over the first barrier metal layer, an ion source layer formed over the dielectric layer, a second barrier metal layer formed over and in electrical contact with the ion source layer, and a first portion of a second metal interconnect layer formed over and in electrical contact with the second barrier metal layer; and

a second resistive random access memory device including a first barrier metal layer formed over and in electrical contact with the second via, an ion source layer formed over the first barrier metal layer, a dielectric layer formed over the ion source layer, a second barrier metal layer formed over and in electrical contact with the ion source layer, and a second portion of the second metal interconnect layer formed over and in electrical contact with the second barrier metal layer.

2. A resistive random access memory cell formed on a semiconductor substrate comprising:

first and second diffused regions disposed in the semiconductor substrate;

a first polysilicon gate layer disposed above, insulated from, and self aligned with inner edges of the first and second diffused regions;

a region of a first metal layer disposed above and insulated from the semiconductor substrate;

a first contact electrically connecting the first diffused region with the region of the first metal layer;

a first resistive random access memory device disposed over and insulated from the region of the first metal layer and having a first terminal and a second terminal, the first resistive random access memory device including a dielectric layer and an ion source layer;

a second resistive random access memory device disposed over and insulated from the region of the first metal layer and having a first terminal and a second terminal, the second resistive random access memory device including a dielectric layer and an ion source layer;

a first conductive plug disposed between and making electrical connection between the first terminal of the first resistive random access memory device and the region of the first metal layer; and

a second conductive plug disposed between and making electrical connection between the first terminal of the second resistive random access memory device and the region of the first metal layer;

a first region of a second metal layer disposed above and insulated from the first metal layer and the first resistive random access memory device;

a second region of the second metal layer disposed above and insulated from the region of the first metal layer and the second resistive random access memory device, the second region of the second metal layer electrically insulated from the first region of the second metal layer;

a third conductive plug disposed between and making electrical connection between the second terminal of the first resistive random access memory device and the first region of the second metal layer; and

a fourth conductive plug disposed between and making electrical connection between the second terminal of the second resistive random access memory device and the second region of the second metal layer.

3. The resistive random access memory cell of claim 2 further comprising:

third and fourth diffused regions disposed in the semiconductor substrate;

a second polysilicon gate layer disposed above, insulated from, and self aligned with inner edges of the third and fourth diffused regions; and

a fifth conductive plug disposed between and making electrical connection between the region of the first metal layer and the second polysilicon gate.

4. The resistive random access memory cell of claim 2 wherein:

the first terminal of the first resistive random access memory device is an anode and the second terminal of the first resistive random access memory device is a cathode; and

the first terminal of the second resistive random access memory device is an anode and the second terminal of the second resistive random access memory device is a cathode.

5. The resistive random access memory cell of claim 2 wherein:

the first terminal of the first resistive random access memory device is an anode and the second terminal of the first resistive random access memory device is a cathode; and

the first terminal of the second resistive random access memory device is a cathode and the second terminal of the second resistive random access memory device is an anode.

6. A resistive random access memory cell formed on a semiconductor substrate comprising:

first and second diffused regions disposed in the semiconductor substrate;

a first polysilicon gate disposed above, insulated from, and self aligned with inner edges of the first and second diffused regions;

a first region of a first metal layer disposed above and insulated from the semiconductor substrate;

a first contact electrically connecting the first diffused region with the first region of the first metal layer;

a first resistive random access memory device disposed over and insulated from the first region of the first metal layer and having a first terminal and a second terminal, the first resistive random access memory device including a dielectric layer and an ion source layer;

a second resistive random access memory device disposed over and insulated from the first region of the first metal layer and having a first terminal and a second terminal, the second resistive random access memory device including a dielectric layer and an ion source layer;

a first region of a second metal layer disposed above and insulated from the first region of the first metal layer and the first resistive random access memory device;

a second region of the second metal layer disposed above and insulated from the first region of the first metal layer and the second resistive random access memory device, the second region of the second metal layer electrically insulated from the first region of the second metal layer;

a first conductive plug disposed between and making electrical connection between the first terminal of the first resistive random access memory device and the first region of the first metal layer;

a second conductive plug disposed between and making electrical connection between the second terminal of the second resistive random access memory device and the second region of the second metal layer;

a third conductive plug disposed between and making electrical connection between the second terminal of the first resistive random access memory device and the first region of the second metal layer; and

a fourth conductive plug disposed between and making electrical connection between the second region of the second metal layer and the first region of the first metal layer.

7. The resistive random access memory cell of claim 6, further comprising:

a second region of the first metal layer electrically insulated from the first region of the first metal layer; and

a fifth conductive plug disposed between and making electrical connection between the first terminal of the first resistive random access memory device and the second region of the first metal layer.

8. The resistive random access memory cell of claim 6, further comprising:

third and fourth diffused regions disposed in the semiconductor substrate;

a second polysilicon gate layer disposed above, insulated from, and self aligned with inner edges of the third and fourth diffused regions; and

a fifth conductive plug disposed between and making electrical connection between the first region of the first metal layer and the second polysilicon gate.

9. The resistive random access memory cell of claim 6, further comprising:

a sixth conductive plug disposed between and making electrical connection between the first region of the first metal layer and the second region of the second metal layer.

10. A resistive random access memory cell formed on a semiconductor substrate comprising:

first and second diffused regions disposed in the semiconductor substrate;

a first polysilicon gate disposed above, insulated from, and self aligned with inner edges of the first and second diffused regions;

a first region of a first metal layer disposed above and insulated from the semiconductor substrate;

a region of a second metal layer disposed above and insulated from the first region of the first metal layer;

a first contact electrically connecting the first diffused region with the first region of the first metal layer;

a first resistive random access memory device disposed above the region of the first metal layer, the first resistive random access memory device having a first terminal and a second terminal, the first resistive random access memory device including a dielectric layer and an ion source layer;

a second resistive random access memory device disposed above the region of the second metal layer, the second resistive random access memory device having a first terminal and a second terminal, the second resistive random access memory device including a dielectric layer and an ion source layer;

a first conductive plug disposed between and making electrical connection between the second terminal of the first resistive random access memory device and the region of the second metal layer;

a second conductive plug disposed between and making electrical connection between the first terminal of the second resistive random access memory device and the region of the second metal layer; and

a third conductive plug disposed between and making electrical connection between the first region of the first metal layer and the region of the second metal layer.

11. The resistive random access memory cell of claim 10, further comprising:

a second region of the first metal layer electrically insulated from the first region of the first metal layer;

a region of a third metal layer disposed above and insulated from the region of the second metal layer;

a fourth conductive plug disposed between and making electrical connection between the first terminal of the first resistive random access memory device and the second region of the first metal layer; and

a fifth conductive plug disposed between and making electrical connection between the second terminal of the second resistive random access memory device and the region of the third metal layer.

12. The resistive random access memory cell of claim 10, further comprising:

third and fourth diffused regions disposed in the semiconductor substrate;

a second polysilicon gate layer disposed above, insulated from, and self aligned with inner edges of the third and fourth diffused regions; and

a sixth conductive plug disposed between and making electrical connection between the first region of the first metal layer and the second polysilicon gate.