Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices

• US 8,415,671 B2
• Filed: 04/16/2010
• Issued: 04/09/2013
• Est. Priority Date: 04/16/2010
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): MOORE, WHITNEY
• Application Number:
  US12/761,518
• Publication Number:
  US 20110254010A1
• Time in Patent Office: 1,089 Days
• Field of Search: 257/66, 257/77, 257/328, 257/192, 257/329, 257/E21.384, 257/E21.41, 257/E29.104, 257/E29.068, 257/E29.201, 257/E29.257, 438/137, 438/270, 438/105, 438/212, 438/285
• US Class Current: 257/66
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor switching devices include a first wide band-gap semiconductor layer having a first conductivity type. First and second wide band-gap well regions that have a second conductivity type that is opposite the first conductivity type are provided on the first wide band-gap semiconductor layer. A non-wide band-gap semiconductor layer having the second conductivity type is provided on the first wide band-gap semiconductor layer. First and second wide band-gap source/drain regions that have the first conductivity type are provided on the first wide band-gap well region. A gate insulation layer is provided on the non-wide band-gap semiconductor layer, and a gate electrode is provided on the gate insulation layer.

Claims

1. A semiconductor switching device, comprising:

a first wide band-gap semiconductor layer having a first conductivity type;

a first wide band-gap well region having a second conductivity type that is opposite the first conductivity type on the first wide band-gap semiconductor layer;

a second wide band-gap well region having the second conductivity type on the first wide band-gap semiconductor layer;

a non-wide band-gap semiconductor layer having the second conductivity type on the first wide band-gap semiconductor layer;

a first wide band-gap source/drain region having the first conductivity type on the first wide band-gap well region;

a second wide band-gap source/drain region having the first conductivity type on the second wide band-gap well region;

a gate insulation layer on the non-wide band-gap semiconductor layer; and

a gate electrode on the gate insulation layer,

wherein the gate insulation layer directly contacts the first wide band-gap well region.

2. The semiconductor switching device of claim 1, wherein the non-wide band-gap semiconductor layer is directly on the first wide band-gap semiconductor layer so as to form a heterojunction with the first wide band-gap semiconductor layer.

3. The semiconductor switching device of claim 2, wherein the heterojunction has a first built-in potential that is lower than a second built-in potential of a homojunction formed between the first wide band-gap semiconductor layer and the first wide band-gap well region.

4. The semiconductor switching device of claim 1, wherein the first wide band-gap semiconductor layer comprises a wide band-gap drift layer.

5. The semiconductor switching device of claim 1, further comprising a wide band-gap current spreading layer below a bottom surface of the first wide band-gap semiconductor layer, wherein the first wide band-gap semiconductor layer comprises a wide band-gap drift layer.

6. The semiconductor switching device of claim 1, wherein the non-wide band-gap semiconductor layer comprises a polysilicon layer.

7. The semiconductor switching device of claim 6, wherein the first wide band-gap semiconductor layer comprises an n-type silicon carbide drift layer, wherein the first and second wide band-gap well regions comprise first and second p-type silicon carbide well regions, wherein the first and second wide band-gap source/drain regions comprise first and second n-type silicon carbide source/drain regions, and wherein the silicon layer comprises a p-type silicon layer.

8. The semiconductor switching device of claim 7, wherein the device further comprises a silicon carbide substrate on the n-type silicon carbide drift layer opposite the first and second p-type silicon carbide well regions.

9. The semiconductor switching device of claim 8, wherein the gate insulation layer is on a top surface of the non-wide band-gap semiconductor layer, and the gate electrode is on a top surface of the gate insulation layer.

10. The semiconductor switching device of claim 9, wherein the silicon carbide substrate comprises an n-type silicon carbide substrate, and the semiconductor switching device comprises a silicon carbide power MOSFET.

11. The semiconductor switching device of claim 9, wherein the silicon carbide substrate comprises a silicon carbide substrate, and the semiconductor switching device comprises a silicon carbide insulated gate bipolar junction transistor (“

IGBT”

).

12. The semiconductor switching device of claim 1, further comprising a second wide band-gap semiconductor region having the second conductivity type between the first wide band-gap semiconductor layer and the non-wide band-gap semiconductor layer, wherein the second wide band-gap semiconductor region having the second conductivity type and the non-wide band-gap semiconductor layer form a heterojunction.

13. The semiconductor switching device of claim 1, further comprising an electrical connection between the non-wide band-gap semiconductor layer and the first and second wide band-gap source/drain regions.

14. The semiconductor switching device of claim 1, wherein a bottom surface of the first wide band-gap well region is on a top surface of the first wide band-gap semiconductor layer, and wherein a bottom surface of the gate electrode is positioned below a top surface of the first wide band-gap well region and below a top surface of the second wide band-gap well region.

15. The semiconductor switching device of claim 1, wherein the non-wide band-gap semiconductor layer does not directly contact either the first wide band-gap well region or the second wide band-gap well region.

16. The semiconductor switching device of claim 1, wherein the gate insulation layer is on a side surface of the first wide band-gap well region and on a side surface of the second wide band-gap well region, the semiconductor switching device further comprising a first channel that extends from a top surface of the first wide band-gap well region to the bottom surface of the first wide band-gap well region and a second channel that extends from a top surface of the second wide band-gap well region to the bottom surface of the second wide band-gap well region.

17. The semiconductor switching device of claim 1, wherein the gate insulation layer directly contacts the first wide band-gap well region.

18. A semiconductor switching device, comprising:

a first wide band-gap semiconductor layer having a first conductivity type;

a first wide band-gap well region having a second conductivity type that is opposite the first conductivity type on a top surface of the first wide band-gap semiconductor layer;

a second wide band-gap well region having the second conductivity type on the top surface of the first wide band-gap semiconductor layer;

a non-wide band-gap semiconductor layer having the second conductivity type on or within the first wide band-gap semiconductor layer;

a first wide band-gap source/drain region having the first conductivity type on the first wide band-gap well region;

a second wide band-gap source/drain region having the first conductivity type on the second wide band-gap well region;

a gate insulation layer on the non-wide band-gap semiconductor layer; and

a gate electrode on the gate insulation layer,

wherein a top surface of the non-wide band-gap semiconductor layer is closer to a bottom surface of the first wide band-gap semiconductor layer than are bottom surfaces of the first and second wide band-gap well regions.

19. The semiconductor switching device of claim 18, wherein the gate insulation layer is on a side surface of the first wide band-gap well region and on a side surface of the second wide band-gap well region, the semiconductor switching device further comprising a first channel that extends from a top surface of the first wide band-gap well region to the bottom surface of the first wide band-gap well region and a second channel that extends from a top surface of the second wide band-gap well region to the bottom surface of the second wide band-gap well region.

20. The semiconductor switching device of claim 18, wherein the non-wide band-gap semiconductor layer does not directly contact either the first wide band-gap well region or the second wide band-gap well region.

21. The semiconductor switching device of claim 18, wherein the gate insulation layer directly contacts the first wide band-gap well region.

22. The semiconductor switching device of claim 18, further comprising a second wide band-gap region having the second conductivity type interposed between the non-wide band-gap semiconductor layer and the first wide band-gap semiconductor layer.

23. The semiconductor switching device of claim 18, further comprising a wide band-gap current spreading layer adjacent a top surface of the first wide band-gap semiconductor layer that has a higher doping concentration than the first wide band-gap semiconductor layer.

24. A semiconductor switching device, comprising:

a first wide band-gap semiconductor layer having a first conductivity type;

a first wide band-gap well region having a second conductivity type that is opposite the first conductivity type on a top surface of the first wide band-gap semiconductor layer;

a second wide band-gap well region second conductivity type on the top surface of the first wide band-gap semiconductor layer;

a non-wide band-gap semiconductor layer having the second conductivity type on the first wide band-gap semiconductor layer,

a first wide band-gap source/drain region having the first conductivity type on the first wide band-gap well region;

a second wide band-gap source/drain region having the first conductivity type on the second wide band-gap well region;

a gate insulation layer on the non-wide band-gap semiconductor layer; and

a gate electrode on the gate insulation layer,

wherein the gate insulation layer is between the non-wide band-gap semiconductor layer and the first wide band-gap well region and between the non-wide band-gap semiconductor layer and the second wide band-gap well region, and the gate electrode is disposed within a first recess in a first portion of the gate insulation layer that is between the non-wide band-gap semiconductor layer and the first wide band-gap well region and within a second recess in a second portion of the gate insulation layer that is between the non-wide band-gap semiconductor layer and the second wide band-gap well region.

25. A method of forming a semiconductor device, comprising:

providing a first wide band-gap semiconductor layer having a first conductivity type on a substrate;

providing a second wide band-gap semiconductor layer having a second conductivity type that is opposite the first conductivity type on the first wide band-gap semiconductor layer;

providing a gate trench that penetrates the second wide band-gap semiconductor layer and a portion of the first wide band-gap semiconductor layer, wherein the gate trench divides the second wide band-gap semiconductor layer into a first wide band-gap well region and a second wide band-gap well region;

providing a first wide band-gap source/drain region having the first conductivity type on the first wide band-gap well region;

providing a second wide band-gap source/drain region having the first conductivity type on the second wide band-gap well region; and

providing a non-wide band-gap semiconductor layer having the second conductivity type in the gate trench and on the first wide band-gap semiconductor layer.

26. The method of claim 25, wherein providing the first and second wide band-gap source/drain regions comprises forming a third wide band-gap semiconductor layer region having the first conductivity type on the second wide band-gap semiconductor layer, and dividing the third wide band-gap semiconductor layer region into the first and second wide band-gap source/drain regions by the formation of the gate trench.

27. The method of claim 25, wherein providing the first and second wide band-gap source/drain regions comprises implanting ions having the first conductivity type into first and second upper portions of the second wide band-gap semiconductor layer.

28. The method of claim 25, further comprising providing a gate insulation layer on sidewalls of the gate trench and on the non-wide band-gap semiconductor layer, and providing a gate electrode on the gate insulation layer.

29. The method of claim 28, wherein the non-wide band-gap semiconductor layer is provided directly on the first wide band-gap semiconductor layer so as to form a heterojunction with the first wide band-gap semiconductor layer.

30. The method of claim 29, wherein the non-wide band-gap semiconductor layer comprises a silicon layer.

31. The method of claim 30, wherein the first wide band-gap semiconductor layer comprises an n-type silicon carbide drift layer or an n-type current spreading layer, wherein the first and second wide band-gap well regions comprise first and second p-type silicon carbide well regions, wherein the first and second wide band-gap source/drain regions comprise first and second n-type silicon carbide source/drain regions, and wherein the silicon layer comprises a p-type silicon layer.

32. The method of claim 31, wherein the substrate comprises an n-type silicon carbide substrate, and the semiconductor switching device comprises a silicon carbide power MOSFET.

33. The method of claim 31, wherein the substrate comprises a p-type silicon carbide substrate, and the semiconductor switching device comprises a power silicon carbide insulated gate bipolar junction transistor (“

IGBT”

).

34. The method of claim 25, further comprising providing a third wide band-gap semiconductor region having the second conductivity type on the first wide band-gap semiconductor layer prior to providing the non-wide band-gap semiconductor layer, wherein the non-wide band-gap semiconductor layer is on the third wide band-gap semiconductor region, and wherein the third wide band-gap semiconductor region and the non-wide band-gap semiconductor layer form a heterojunction.

35. The method of claim 25, further comprising providing an electrical connection between the non-wide band-gap semiconductor layer and the first and second wide band-gap source/drain regions.

36. A semiconductor device, comprising:

a first wide band-gap semiconductor layer;

a gate insulation layer on the first wide band-gap semiconductor layer;

a gate electrode adjacent the gate insulation layer;

a non-wide band-gap semiconductor pattern that is on the first wide band-gap semiconductor layer;

a first wide band-gap semiconductor well region having the second conductivity type on a top surface of the first wide band-gap semiconductor layer, the first wide band-gap semiconductor well region including a first channel region therein; and

a second wide band-gap semiconductor well region having the second conductivity type on the top surface of the first wide band-gap semiconductor layer, the second wide band-gap semiconductor well region including a second channel region therein,

wherein a bottom surface of the non-wide band-gap semiconductor pattern is closer to a bottom surface of the first wide band-gap semiconductor layer than are the first and second channel regions.

37. The semiconductor device of claim 36, wherein the non-wide band-gap semiconductor pattern is directly on the first wide band-gap semiconductor layer so as to form a heterojunction with the first wide band-gap semiconductor layer.

38. The semiconductor device of claim 37, wherein the gate electrode includes opposed sidewalls, and wherein at least a portion of the non-wide band-gap semiconductor pattern is between the opposed sidewalls of the gate electrode.

39. The semiconductor device of claim 37, wherein the gate electrode is at least partially positioned within a gate trench that extends below a top surface of the first wide band-gap semiconductor well region and below a top surface of the second wide band-gap semiconductor well region so that a bottom portion of the gate electrode is positioned in a bottom portion of the gate trench between the first and second wide band-gap semiconductor well regions, and wherein the non-wide band-gap semiconductor pattern is positioned between the bottom portion of the gate electrode and the first wide band-gap semiconductor layer.

40. The semiconductor device of claim 36, wherein the first wide band-gap semiconductor layer has a first conductivity type, and wherein the non-wide band-gap semiconductor pattern has a second conductivity type that is different from the first conductivity type.

41. The semiconductor device of claim 40, further comprising a wide band-gap semiconductor pattern having the second conductivity type between at least a portion of the first wide band-gap semiconductor layer and the non-wide band-gap semiconductor pattern, wherein the second wide band-gap semiconductor pattern and the non-wide band-gap semiconductor pattern form a heterojunction, wherein wide band-gap semiconductor pattern having the second conductivity type is positioned closer to the bottom surface of the first wide band-gap semiconductor layer than are the first and second wide band-gap semiconductor well regions.

42. The semiconductor device of claim 40, further comprising:

a first wide band-gap semiconductor source/drain region having the first conductivity type on the first wide band-gap semiconductor well region; and

a second wide band-gap semiconductor source/drain region having the first conductivity type on the second wide band-gap semiconductor well region.

43. The semiconductor device of claim 42, further comprising an electrical connection between the non-wide band-gap semiconductor pattern and the first and second wide band-gap semiconductor source/drain regions.

44. The semiconductor switching device of claim 36, wherein the non-wide band-gap semiconductor pattern comprises a silicon pattern, and wherein the first wide band-gap semiconductor layer comprises a silicon carbide layer.

45. The semiconductor switching device of claim 36, wherein a bottom surface of the non-wide band-gap semiconductor layer is closer to a bottom surface of the first wide band-gap semiconductor layer than is a bottom surface of the first wide band-gap well region.

46. The semiconductor switching device of claim 36, wherein the first wide band-gap well region is on a top surface of the first wide band-gap semiconductor layer and the gate insulating layer is on a side surface of the first wide band-gap well region and on a side surface of the second wide band-gap well region, the semiconductor switching device further comprising a first channel that extends from a top surface of the first wide band-gap well region to the bottom surface of the first wide band-gap well region and a second channel that extends from a top surface of the second wide band-gap well region to the bottom surface of the second wide band-gap well region.

47. The semiconductor switching device of claim 36, wherein the gate insulation layer directly contacts the first wide band-gap well region.

48. The semiconductor switching device of claim 36, wherein a bottom surface of the non-wide band-gap semiconductor layer is closer to a bottom surface of the first wide band-gap semiconductor layer than is a bottom surface of the first wide band-gap well region.

49. The semiconductor device of claim 36, wherein the non-wide band-gap semiconductor pattern that is between the first wide band-gap semiconductor layer and at least a portion of the gate insulation layer.