Semiconductor device and method for manufacturing the same

• US 8,415,711 B2
• Filed: 09/15/2011
• Issued: 04/09/2013
• Est. Priority Date: 09/21/2010
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kitagawa, Mitsuhiko
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US13/234,061
• Publication Number:
  US 20120074460A1
• Time in Patent Office: 572 Days
• Field of Search: 257/139, 257/334, 257/E21.09, 257/E21.41, 257/29.262, 438/270, 438/478
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

According to an embodiment, a semiconductor device includes a first trench being provided in an N⁺ substrate. An N layer, an N⁻ layer, a P layer, and an N⁺ layer are formed in a stacked manner to cover the first trench. The semiconductor device includes second and third trenches. The P⁺ layer is formed to cover the second trench. The trench gates are formed to cover the third trenches.

Claims

1. A semiconductor device, comprising:

a first trench provided in a semiconductor substrate of a first conductivity type;

a first semiconductor layer of the first conductivity type having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type having an impurity concentration higher than that of the first semiconductor layer, the first to third semiconductor layers being formed in a stacked manner to cover the first trench;

a second trench provided in the third semiconductor layer in such a manner that the second trench at least partially penetrates the third semiconductor layer to expose the second semiconductor layer in a vertical direction relative to a plane of the semiconductor substrate, and at least partially penetrates the third semiconductor layer to expose the second semiconductor layer in a horizontal direction relative to the plane of the semiconductor substrate;

a fourth semiconductor layer of the second conductivity type having an impurity concentration higher than that of the second semiconductor layer, the fourth semiconductor layer being formed to cover the second trench;

third trenches arranged between portions of the fourth semiconductor layer in such a manner as to be spaced apart from the side of the fourth semiconductor layer, the third trenches being provided so that each of the trenches penetrates the third semiconductor layer to expose the second semiconductor layer or penetrates the third and second semiconductor layers to expose the first semiconductor layer in the vertical direction relative to the plane of the semiconductor substrate, and so that each of the trenches penetrates the second semiconductor layer to expose the first semiconductor layer on one end or penetrates the second and first semiconductor layers to expose the semiconductor substrate on one end and to expose the third semiconductor layer on the other end in the horizontal direction relative to the plane of the semiconductor substrate; and

trench gates formed to cover the third trenches, each trench gate including a gate insulating film and a gate electrode film formed in a stacked manner.

2. The semiconductor device according to claim 1, wherein

the third and fourth semiconductor layers are connected to a source electrode,

the semiconductor substrate is connected to a drain electrode, and

when the semiconductor device is turned on, a channel layer is formed on the side of the trench gate in the vertical direction of the semiconductor substrate, and carriers flow through the channel layer from a source toward a drain.

3. The semiconductor device according to claim 1, wherein carriers are generated in the first semiconductor layer near the interface of the first and second semiconductor layers when the semiconductor device breaks down, the carriers are withdrawn to a source electrode through the second and fourth semiconductor layers.

4. The semiconductor device according to claim 1, wherein the semiconductor substrate is a first drain layer of an N type having a high impurity concentration, the first semiconductor layer is a second drain layer of the N type having an impurity concentration lower than that of the first drain, and the third semiconductor layer is a source layer of the N type having a high impurity concentration.

5. The semiconductor device according to claim 1, wherein the semiconductor substrate is a first drain layer of an N type having a high impurity concentration, the first semiconductor layer includes a second drain layer and a drift layer, the second drain layer of the N type has an impurity concentration lower than that of the first drain layer, the drift layer of the N type having an impurity concentration lower than that of the second drain layer, and the third semiconductor layer is a source layer of the N type having a high impurity concentration.

6. The semiconductor device according to claim 1, wherein the fourth semiconductor layer is a carrier withdrawal layer to withdraw carriers generated by the breakdown of the semiconductor device.

7. The semiconductor device according to claim 1, wherein the semiconductor device is an N-channel power MOS transistor.

8. The semiconductor device according to claim 1, further comprising

a field plate provided in the third trench in such a manner as to face the trench gate with an insulating film interposed therebetween so as to cover the third trench at the first semiconductor layer side.

9. The semiconductor device according to claim 8, wherein the field plate is connected to a source electrode.

10. The semiconductor device according to claim 8, wherein the field plate is composed of an N⁺ polycrystalline silicon film, a metal film, or a metal silicide film.

11. A semiconductor device, comprising:

a first trench provided in a semiconductor substrate of a first conductivity type;

a first semiconductor layer of a second conductivity type, a second semiconductor layer of the second conductivity type having an impurity concentration lower than that of the first semiconductor layer, a third semiconductor layer of the first conductivity type having an impurity concentration lower than that of the semiconductor substrate, and a fourth semiconductor layer of the second conductivity type having an impurity concentration higher than that of the second semiconductor layer, the first to fourth semiconductor layers being formed in a stacked manner to cover the first trench;

a second trench provided in the fourth semiconductor layer in such a manner that the second trench at least partially penetrates the fourth semiconductor layer to expose the third semiconductor layer in a vertical direction relative to a plane of the semiconductor substrate, and at least partially penetrates the fourth semiconductor layer to expose the third semiconductor layer in a horizontal direction relative to the plane of the semiconductor substrate;

a fifth semiconductor layer of the first conductivity type having an impurity concentration higher than that of the third semiconductor layer, the fifth semiconductor layer being formed to cover the second trench;

third trenches arranged between portions of the fifth semiconductor layer in such a manner as to be spaced apart from the side of the fifth semiconductor layer, the third trenches being provided so that each of the trenches penetrates the fourth semiconductor layer to expose the third semiconductor layer or penetrates the fourth and third semiconductor layers to expose the second semiconductor layer in the vertical direction relative to the plane of the semiconductor substrate, and so that each of the trenches penetrates the third semiconductor layer to expose the second semiconductor layer on one end or penetrates the third and second semiconductor layers to expose the first semiconductor layer on one end and to expose the fourth semiconductor layer on the other end in the horizontal direction relative to the plane of the semiconductor substrate; and

trench gates formed to cover the third trenches, each trench gate including a gate insulating film and a gate electrode film formed in a stacked manner.

12. The semiconductor device according to claim 11, wherein

the fourth and fifth semiconductor layers are connected to an emitter electrode,

the semiconductor substrate is connected to a collector electrode, and

when the semiconductor device is turned on, a channel layer is formed on the side of the trench gate in the vertical direction of the semiconductor substrate, and carriers flow through the channel layer from an emitter toward a collector.

13. The semiconductor device according to claim 11, wherein carriers are generated in the second semiconductor layer near the interface of the second and third semiconductor layers when the semiconductor device breaks down, the carriers are withdrawn to the emitter electrode through the third and fifth semiconductor layers.

14. The semiconductor device according to claim 11, wherein the semiconductor substrate is a first collector layer of a P type having a high impurity concentration, the first semiconductor layer is a second collector layer of an N type having a high impurity concentration, the second semiconductor layer includes a buffer layer and a first base layer, the buffer layer of the N type has an impurity concentration lower than that of the second collector layer, the first base layer of the N type has an impurity concentration lower than that of the first collector layer, the third semiconductor layer is a second base layer of the P type having an impurity concentration lower than that of the first collector layer, and the fourth semiconductor layer is an emitter layer of the N type having a high impurity concentration.

15. The semiconductor device according to claim 11, wherein the fifth semiconductor layer is a carrier withdrawal layer to withdraw carriers generated by the breakdown of the semiconductor device.

16. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first trench in a semiconductor substrate of a first conductivity type, the first trench having a quadrangular prism shape elongated in a horizontal direction relative to a plane of the semiconductor substrate;

forming a first semiconductor layer of the first conductivity type having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type having an impurity concentration higher than that of the first semiconductor layer, the first to third semiconductor layers being formed in a stacked manner to cover the first trench;

polishing the first to third semiconductor layers to be flattened so that the semiconductor substrate is exposed;

forming a second trench in the third semiconductor layer in such a manner that the second trench at least partially penetrates the third semiconductor layer to expose the second semiconductor layer in a vertical direction relative to the plane of the semiconductor substrate, and at least partially penetrates the third semiconductor layer to expose the second semiconductor layer in the horizontal direction relative to the plane of the semiconductor substrate;

forming a fourth semiconductor layer of the second conductivity type having an impurity concentration higher than that of the second semiconductor layer, the fourth semiconductor layer being formed to cover the second trench;

polishing the fourth semiconductor layer to be flattened so that the semiconductor substrate is exposed;

forming third trenches in such a manner that the third trenches are spaced apart from the fourth semiconductor layer, the third trenches being formed so that each of the trenches penetrates the third and second semiconductor layers formed in the stacked manner to expose the first semiconductor layer in the vertical direction relative to the plane of the semiconductor substrate, and so that each of the trenches penetrates the second semiconductor layer to expose the first semiconductor layer or the semiconductor substrate on one end and to expose the third semiconductor layer on the other end in the horizontal direction relative to the plane of the semiconductor substrate; and

forming trench gates in such a manner that the trench gates cover the third trenches, each trench gate including a gate insulating film and a gate electrode film.

17. The method for manufacturing a semiconductor device, according to claim 16, wherein the first to fourth semiconductor layers are formed using an epitaxial method.

18. The method for manufacturing a semiconductor device, according to claim 16, wherein the polishing for flattening is performed using a CMP method.

19. The method for manufacturing a semiconductor device, according to claim 16, wherein the first to third trenches are formed using an RIE method.

20. The method according to claim 16, wherein the semiconductor device is an N-channel power MOS transistor.