Method of forming epi film in substrate trench

• US 8,415,718 B2
• Filed: 05/20/2010
• Issued: 04/09/2013
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Xu, Jeff J.
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US12/784,207
• Publication Number:
  US 20110101421A1
• Time in Patent Office: 1,055 Days
• Field of Search: 257/255
• US Class Current: 257/255
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate

Abstract

The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a semiconductor substrate;

forming a trench in the substrate, wherein a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation; and

epitaxially (epi) growing a semiconductor material in the trench;

wherein the epi process utilizes an etch component, and wherein a first growth rate on the first crystal plane orientation is greater than a second growth rate on the second crystal plane orientation.

2. The method of claim 1, wherein the semiconductor material includes one of silicon (Si), silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), and III-V compound semiconductor.

3. The method of claim 1, wherein the etch component includes one of a Cl containing gas and a Br containing gas.

4. The method of claim 1, wherein the substrate includes one of silicon (Si) and germanium (Ge).

5. The method of claim 1, wherein the first crystal plane orientation includes [100] and wherein the second crystal plane orientation includes one of [110] and [111].

6. The method of claim 2, wherein the III-V compound semiconductor includes one of GaAs and InSb.

7. The method of claim 3, wherein the etch component includes HCl.

8. A method of fabricating a semiconductor device, comprising:

forming a transistor on a semiconductor substrate including;

a gate structure disposed over the substrate;

a trench in the semiconductor substrate adjacent the gate structure, wherein a bottom surface of the trench has a first crystal plane orientation of the substrate, and two opposing side surfaces of the trench have a second crystal plane orientation of the substrate, the first crystal plane orientation being different from the second crystal plane orientation; and

a strained feature formed within the trench on the substrate, wherein the strained feature is formed by growing an epi film by a bottom-up growth process such that the epi is grown predominately from the bottom surface of a trench in the semiconductor substrate and a side surface of the epi-film is substantially free of dislocation defects.

9. The method of claim 8, wherein the first crystal plane orientation includes [100] and wherein the second crystal plane orientation includes one of [110] and [111].

10. The method of claim 9, wherein the epi film includes Ge and wherein the transistor includes a PMOS device.

11. The method of claim 10, wherein the transistor includes a FinFET and wherein the strained feature forms a portion of a fin.

12. The method device of claim 10, wherein the transistor includes a planar FET.

13. A method of fabricating a semiconductor device, comprising:

providing a semiconductor substrate;

forming a trench in the substrate, wherein a first surface of the trench has a first crystal plane orientation and a second surface of the trench has a second crystal plane orientation; and

performing an epitaxial (epi) growth process to grow an epi film in the trench, the epi growth process incorporating an etch component;

wherein a first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation such that the etch component prohibits growth on one of the first and second crystal plane orientations.

14. The method of claim 13, wherein the first growth rate is greater than the second growth rate.

15. The method of claim 13, wherein the semiconductor material includes one of silicon (Si), silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), and III-V compound semiconductor.

16. The method of claim 15, wherein the semiconductor substrate includes silicon (Si).

17. The method of claim 16, wherein the etch component includes one of a Cl containing gas and a Br containing gas.