Semiconductor storage device with integrated capacitor and having transistor overlapping sections

• US 8,415,731 B2
• Filed: 12/27/2010
• Issued: 04/09/2013
• Est. Priority Date: 01/20/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): Pizarro, Marcos D.
• Assistant Examiner(s): Lpez, Csar
• Application Number:
  US12/978,759
• Publication Number:
  US 20110175087A1
• Time in Patent Office: 834 Days
• Field of Search: None
• US Class Current: 257/300
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

To provide a storage device in which advantages of both a nonvolatile storage device and a volatile storage device can be obtained, a semiconductor device includes a first transistor provided in or over a substrate and a second transistor provided above the first transistor, where at least part of the first transistor and the second transistor are overlapped with each other, and a gate electrode of the first transistor and a source or drain electrode of the second transistor are electrically connected to each other. It is preferable that the first transistor be provided using single crystal silicon and the second transistor be provided using an oxide semiconductor having extremely low off-state current.

Claims

1. A semiconductor device comprising:

a first transistor comprising;

a first channel formation region including a first semiconductor material;

impurity regions provided with the first channel formation region interposed therebetween;

a first gate insulating layer provided over the first channel formation region;

a first gate electrode overlapping with the first channel formation region and is provided over the first gate insulating layer; and

a first source or drain electrode electrically connected to one of the impurity regions, and

a second transistor comprising;

a second source electrode;

a second drain electrode;

a second channel formation region including a second semiconductor material and electrically connected to the second source electrode and the second drain electrode;

a second gate insulating layer provided over the second channel formation region; and

a second gate electrode overlapping with the second channel formation region and provided over the second gate insulating layer,

wherein the first semiconductor material comprises a single crystal semiconductor layer provided over an insulating surface,

wherein the second semiconductor material is an oxide semiconductor,

wherein the first transistor and the second transistor are provided so that at least part thereof overlap with each other, and

wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode.

2. The semiconductor device according to claim 1, wherein the first semiconductor material and the second semiconductor material are different.

3. The semiconductor device according to claim 1 wherein a plurality of insulating layers is provided between the first transistor and the second transistor and at least an insulating layer of the plurality of insulating layers, which is in contact with the second transistor, is formed with a sputtering method.

4. The semiconductor device according to claim 1, wherein an energy gap of the second semiconductor material is higher than 3 eV.

5. The semiconductor device according to claim 1, wherein the first transistor is capable of operating at higher speed than the second transistor.

6. The semiconductor device according to claim 1, further comprising, sidewall insulating layers provided in contact with side surfaces of the first gate electrode.

7. The semiconductor device according to claim 1, wherein the first gate electrode is in direct contact with one of the second source electrode and the second drain electrode.

8. The semiconductor device according to claim 1, wherein an off-state current of the second transistor is lower than an off-state current of the first transistor.

9. The semiconductor device according to claim 8, wherein an off-state current of the second transistor at room temperature is less than or equal to 10 zA.

10. A semiconductor device comprising:

a first transistor comprising;

a first channel formation region including a first semiconductor material;

impurity regions provided with the first channel formation region interposed therebetween;

a first gate insulating layer provided over the first channel formation region;

a first gate electrode which overlapping with the first channel formation region and provided over the first gate insulating layer; and

a first source or drain electrode electrically connected to one of the impurity regions,

a second transistor comprising;

a second source electrode;

a second drain electrode;

a second channel formation region including a second semiconductor material and electrically connected to the second source electrode and the second drain electrode;

a second gate insulating layer provided over the second channel formation region; and

a second gate electrode overlapping with the second channel formation region and provided over the second gate insulating layer, and

a capacitor comprising;

one of the second source electrode and the second drain electrode;

the second gate insulating layer; and

an electrode for the capacitor provided over the second gate insulating layer,

wherein the first semiconductor material comprises a single crystal semiconductor layer provided over an insulating surface,

wherein the first transistor and the second transistor are provided so that at least part thereof overlap with each other, and

wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode.

11. The semiconductor device according to claim 10, wherein the first semiconductor material and the second semiconductor material are different.

12. The semiconductor device according to claim 10, wherein an energy gap of the second semiconductor material is higher than 3 eV.

13. The semiconductor device according to claim 10, wherein the first transistor is capable of operating at higher speed than the second transistor.

14. The semiconductor device according to claim 10, wherein the capacitor further comprises a semiconductor layer including the second semiconductor material.

15. The semiconductor device according to claim 10, further comprising, sidewall insulating layers provided in contact with side surfaces of the first gate electrode.

16. The semiconductor device according to claim 10, wherein the first gate electrode is in direct contact with one of the second source electrode and the second drain electrode.

17. The semiconductor device according to claim 10, wherein the second semiconductor material is an oxide semiconductor.

18. The semiconductor device according to claim 17, wherein a plurality of insulating layers is provided between the first transistor and the second transistor and at least an insulating layer of the plurality of insulating layers, which is in contact with the second transistor, is formed with a sputtering method.

19. The semiconductor device according to claim 10, wherein an off-state current of the second transistor is lower than an off-state current of the first transistor.

20. The semiconductor device according to claim 19, wherein an off-state current of the second transistor at room temperature is less than or equal to 10 zA.

21. A semiconductor device comprising:

a first transistor comprising;

a first channel formation region including a first semiconductor material;

a first gate insulating layer;

a first gate electrode; and

a first source and drain electrode,

a second transistor comprising;

a second source electrode;

a second drain electrode;

a second channel formation region including a second semiconductor material;

a second gate insulating layer; and

a second gate electrode,

an insulating layer provided over and in contact with the first transistor, and

a capacitor comprising;

one of the second source electrode and the second drain electrode;

the second gate insulating layer; and

an electrode for the capacitor provided over the second gate insulating layer,

wherein the first semiconductor material comprises a single crystal semiconductor layer provided over an insulating surface,

wherein the second transistor provided over the insulating layer,

wherein the first gate electrode is exposed from a top surface of the insulating layer, and

wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode.

22. The semiconductor device according to claim 21, wherein the first semiconductor material and the second semiconductor material are different.

23. The semiconductor device according to claim 21, wherein the second semiconductor material is an oxide semiconductor.

24. The semiconductor device according to claim 21, wherein the insulating layer comprises a plurality of insulating layers.

25. The semiconductor device according to claim 21, wherein an energy gap of the second semiconductor material is higher than 3 eV.

26. The semiconductor device according to claim 21, wherein the first transistor is capable of operating at higher speed than the second transistor.

27. The semiconductor device according to claim 21, wherein the capacitor further comprises a semiconductor layer including the second semiconductor material.

28. The semiconductor device according to claim 21, further comprising, sidewall insulating layers provided in contact with side surfaces of the first gate electrode.

29. The semiconductor device according to claim 21, wherein the first gate electrode is in direct contact with one of the second source electrode and the second drain electrode.

30. The semiconductor device according to claim 21, wherein an off-state current of the second transistor is lower than an off-state current of the first transistor.

31. The semiconductor device according to claim 30, wherein an off-state current of the second transistor at room temperature is less than or equal to 10 zA.