Memory device protection layer

• US 8,415,734 B2
• Filed: 12/07/2006
• Issued: 04/09/2013
• Est. Priority Date: 12/07/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Thurgate, Timothy, Yang, Jean Yee-Mei, Brennan, Michael, Sugino, Rinji
• Primary Examiner(s): HUBER, ROBERT T
• Application Number:
  US11/608,032
• Publication Number:
  US 20080135913A1
• Time in Patent Office: 2,315 Days
• Field of Search: 257/324, 257/325, 257/E27.103, 257/E29.309, 257/314, 257/315
• US Class Current: 257/314
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.

Claims

1. A memory device, comprising:

a substrate;

a plurality of memory cells, each memory cell, of the plurality of memory cells, including;

a first dielectric layer formed over the substrate,

a charge storage layer formed over the first dielectric layer,

the charge storage layer including a nitride,

a second dielectric layer formed over the charge storage layer, and

a control gate layer formed over the second dielectric layer;

a plurality of source regions formed in the substrate, each source region, of the plurality of source regions, being formed adjacent to a first side of each memory cell of the plurality of memory cells;

a plurality of drain regions formed in the substrate, each drain region, of the plurality of drain regions, being formed adjacent to a second side, of each of the plurality of memory cells, that is opposite the first side;

a protection layer formed on;

a top surface of each of the plurality of source regions, a top surface of each of the plurality of drain regions, the first dielectric layer of each of the plurality of memory cells, the charge storage layer of each of the plurality of memory cells, the second dielectric layer of each of the plurality of memory cells, and the control gate layer of each of the plurality of memory cells,

the protection layer including oxynitride, and

a thickness of the protection layer ranging from about 50 Å

to about 150 Å

;

spacers formed;

in contact with the protection layer, and

on opposite sides of each of the plurality of memory cells;

a third dielectric layer formed over each of the plurality of memory cells and the spacers, the third dielectric layer contacting;

a top of surface of the control gate layer, of each of the plurality of memory cells, and a portion of the spacers; and

a contact formed between each of the plurality of memory cells, the contact contacting the spacers and the third dielectric layer, and the contact not substantially contacting the plurality of memory cells.

2. The memory device of claim 1, where the protection layer comprises a dielectric material that minimizes diffusion of oxygen, and

where the protection layer at least one of minimizes or prevents formation of bird'"'"'s beaks below the plurality of memory cells.

16. The memory device of claim 1, further comprising:

a liner layer formed in contact with;

the top surface of the source region,

the top surface of the drain region, and

side surfaces of each of the plurality of memory cells,

the liner layer being formed between the protection layer and each of the plurality of memory cells.

3. A memory device, comprising:

a substrate;

a first dielectric layer formed over the substrate;

a charge storage layer formed over the first dielectric layer;

a second dielectric layer formed over the charge storage layer;

a control gate layer formed over the second dielectric layer;

a source region formed in the substrate;

a drain region formed in the substrate;

a liner layer formed on;

a top surface of the source region,

a top surface the drain region, and

side surfaces of the first dielectric layer, the charge storage layer, the second dielectric layer, and the control gate layer, the liner layer contacting one or more of the first dielectric layer, the charge storage layer, the second dielectric layer, or the control gate layer;

a protection layer formed on side surfaces of the liner layer;

spacers formed;

in contact with the protection layer, and

on opposite sides of the first dielectric layer, the charge storage layer, the second dielectric layer, and the control gate layer;

a third dielectric layer formed over the first dielectric layer, the charge storage layer, the second dielectric layer, the control gate layer, and the spacers, the third dielectric layer contacting;

a top of surface of the control gate layer, and

a portion of the spacers; and

a contact formed in contact with one of the spacers and a portion of the third dielectric layer, the contact not substantially contacting the first dielectric layer, the charge storage layer, the second dielectric layer, and the control gate layer.

4. The memory device of claim 3, where a thickness of the liner layer ranges from about 50 Å

to about 500 Å

.

5. The memory device of claim 3, where a thickness of the liner layer ranges from about 50 Å

to about 500 Å

.

6. The memory device of claim 3, where the protection layer:

comprises a dielectric material that minimizes diffusion of oxygen at least one of minimizes or prevents non-uniform thickening of one or more of the first dielectric layer or the second dielectric layer, and

at least one of minimizes or prevents mobile ion penetration in the memory device from back end of line (BEOL) processing.

7. The memory device of claim 3, where a thickness of the protection layer ranges from about 50 Å

to about 500 Å

.

8. The memory device of claim 3, where a thickness of the protection layer ranges from about 50 Å

to about 500 Å

.

9. A memory device, comprising:

a plurality of memory cells formed on a substrate, each memory cell, of the plurality of memory cells, being associated with a source region and a drain region that are formed in the substrate, at least one of the plurality of memory cells comprising;

a first dielectric layer formed over the substrate,

a charge storage layer formed over the first dielectric layer,

a second dielectric layer formed over the charge storage layer, and

a control gate layer formed over the second dielectric layer;

a protection layer formed;

above a top surface of the source region associated with each of the plurality of memory cells, a top surface of the drain region associated with each of the plurality of memory cells, and on side surfaces of each of the plurality of memory cells;

spacers formed in contact with the protection layer and on opposite sides of each of the plurality of memory cells, the protection layer being formed between each of the spacers and a corresponding side surface of each of the plurality of memory cells;

a third dielectric layer formed over each of the plurality of memory cells and the spacers, the third dielectric layer contacting;

a top of surface of each of the plurality of memory cells, and

a portion of the spacers; and

a contact formed between each of the plurality of memory cells, the contact contacting the spacers, and the contact not substantially contacting the plurality of memory cells.

10. The memory device of claim 9, where a thickness of the protection layer ranges from about 50 Å

to about 500 Å

.

11. The memory device of claim 9, where a thickness of the protection layer ranges from about 50 Å

to about 500 Å

.

12. The memory device of claim 9, further comprising:

a liner layer formed;

directly on the top surfaces of the source regions and the drain regions associated with the plurality of memory cells, and

on the side surfaces of the plurality of memory cells, the liner layer being formed between the protection layer and each of the plurality of memory cells, the protection layer being formed on a top surface of the liner layer, the protection layer including oxynitride.

13. The memory device of claim 12, where the liner layer comprises an oxide.

14. The memory device of claim 12, where a thickness of the liner layer ranges from about 50 Å

to about 500 Å

.

15. The memory device of claim 12, where a thickness of the liner layer ranges from about 50 Å

to about 500 Å

.