Apparatus and methodology for testing stacked die

• US 8,415,783 B1
• Filed: 10/04/2007
• Issued: 04/09/2013
• Est. Priority Date: 10/04/2007
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Rahman, Arifur, Chaware, Raghunandan
• Primary Examiner(s): Matthews, Colleen
• Assistant Examiner(s): Yushina, Galina
• Application Number:
  US11/973,245
• Time in Patent Office: 2,014 Days
• Field of Search: 257/686, 257/678, 257/E25.01, 257/E25.006, 257/E25.013, 257/E23.085, 257/620, 257/48, 257/E21.524, 257/734, 257/725, 257/723
• US Class Current: 257/686
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15172 Fan-out arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A packaged integrated circuit (“IC”) has a daughter IC die stacked on a backside of a parent IC die. Backside fill material is applied to the backside of the parent IC die to provide a planarized surface.

Claims

1. A testable wafer structure, comprising:

a wafer having a plurality of parent integrated circuit (IC) dice formed thereon;

wherein each parent IC die has a front side, a backside, and a via extending to a pad on the backside of the parent IC die;

a plurality of daughter IC dice, each daughter IC die being stacked on the backside of a respective one of the parent IC dice and electrically connected to the one of the parent IC dice through the pad of the one of the parent IC dice;

a plurality of silicon wafer portions, each wafer portion disposed on edge on the backside of a respective one of the plurality of parent IC dice, and further disposed between adjacent ones of the daughter dice; and

backside fill material disposed on the backsides of the plurality of parent IC dice on the wafer, wherein the backside fill material in areas between a plurality of pairs of the plurality of daughter dice forms a continuous planar surface.

2. The testable wafer structure of claim 1 wherein the via is a through via extending from the front side of the parent IC die to the backside of the parent IC die.

3. The testable wafer structure of claim 1 wherein the daughter IC die is electrically connected to the pad of the parent IC die with a micro bump.

4. The testable wafer structure of claim 1 wherein the parent IC die is a field programmable gate array (“

FPGA”

) die and the via extends to an intermediate metal layer of the FPGA die.

5. The testable wafer structure of claim 1 wherein the backside fill material comprises molding compound.

6. The testable wafer structure of claim 1 wherein the backside fill material comprises between eighty volume percent and ninety volume percent silica fill in an epoxy matrix.

7. The testable wafer structure of claim 1 further comprising a second plurality of daughter IC dice, each daughter IC die of the second plurality being stacked on the backside of a respective one of the plurality of parent IC dice.

8. The testable wafer structure of claim 1, wherein each of the plurality of daughter IC dice is thicker than each of the plurality of parent IC dice.

9. The testable wafer structure of claim 1, wherein the continuous planar surface formed by the backside fill material is continuously planar with tops of the plurality of daughter IC dice.

10. A testable wafer structure, comprising:

a wafer having a plurality of parent integrated circuit (IC) dice formed thereon;

wherein each parent IC die has a front side, a backside, and a via extending to a pad on the backside of the parent IC die;

a plurality of daughter IC dice, each daughter IC die being stacked on the backside of a respective one of the parent IC dice and electrically connected to the parent IC die through the pad;

a plurality of silicon wafer portions, each wafer portion disposed on edge on the backside of a respective one of the plurality of parent IC dice, and further disposed between adjacent ones of the daughter dice;

one or more dummy dice attached to the backsides of one or more of the parent IC dice, respectively; and

backside fill material disposed on the backsides of the plurality of parent IC dice on the wafer, wherein the backside fill material in areas between a plurality of pairs of the plurality of daughter dice forms a continuous planar surface with tops of the one or more dummy dice.

11. The testable wafer structure of claim 10, wherein the one or more dummy dice are thicker than the daughter dice.

12. The testable wafer structure of claim 10, wherein the one or more dummy dice are thinner than the daughter dice.

13. The testable wafer structure of claim 10, wherein the one or more dummy dice are equal in thickness to the daughter dice.

14. The testable wafer structure of claim 10, further comprising a second plurality of daughter IC dice, each daughter IC die of the second plurality stacked on the backside of a respective one of the plurality of parent IC dice.

15. A testable wafer structure, comprising:

a wafer having a plurality of parent integrated circuit (IC) dice formed thereon;

wherein each parent IC die has a front side, a backside, and a via extending from an intermediate metal layer of the parent IC die to a pad on the backside of the parent IC die;

a plurality of daughter IC dice, each daughter IC die being stacked on the backside of a respective one of the parent IC dice and electrically connected to the one of the parent IC dice through the pad of the one of the parent IC dice;

a plurality of silicon wafer portions, each wafer portion disposed on edge on the backside of a respective one of the plurality of parent IC dice, and further disposed between adjacent ones of the daughter dice; and

backside fill material disposed on the backsides of the plurality of parent IC dice on the wafer, wherein the backside fill material in areas between a plurality of pairs of the plurality of daughter dice forms a continuous planar surface.

16. The testable wafer structure of claim 15, wherein the pad is disposed between the backside of the parent IC die and a front side of the daughter IC die.

17. The testable wafer structure of claim 15, further comprising a silicon fill disposed on the backsides of the parent IC dice.

18. The testable wafer structure of claim 15, further comprising a second plurality of daughter IC dice, each daughter IC die of the second plurality stacked on the backside of a respective one of the plurality of parent IC dice.