Configurable integrated circuit with built-in turns

• US 8,415,973 B2
• Filed: 07/22/2011
• Issued: 04/09/2013
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Rohe, Andre, Teig, Steven
• Primary Examiner(s): Ismail, Shawki
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US13/189,486
• Publication Number:
  US 20120062278A1
• Time in Patent Office: 627 Days
• Field of Search: 326 37- 41, 326/47, 326/101, 716/100, 716/110, 716/116, 716/118
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments of the invention provide an integrated circuit (“IC”) that includes numerous configurable nodes arranged in an array having several rows and columns. In some embodiments, the configurable nodes include a first group of configurable aligned along a particular direction and a second group of configurable nodes aligned along a different direction. The IC also includes a set of direct offset turn connections arranged across the node array in a repetitive nested architecture. Each direct offset turn connection connects a node from the first group of configurable nodes to a node from the second group of configurable nodes. Each direct offset turn connection includes at least two wire segments that are arranged in at least two different directions and intersect to define a turn. No direct offset turn connection overlaps with another direct offset turn connection.

Claims

1. An integrated circuit (“

IC”

) comprising;

a plurality of configurable nodes arranged in an array having a plurality of rows and a plurality of columns, the plurality of configurable nodes comprising a first group of configurable nodes aligned along a first direction and a second group of configurable nodes aligned along a second direction, wherein the first direction and second direction intersect at a particular location;

a set of nested direct offset connections comprising (i) a first direct offset connection that connects a first node from the first group of configurable nodes with a second node from the second group of configurable nodes, and (ii) a second direct offset connection that connects a third node from the first group of configurable nodes with a fourth node from the second group of configurable nodes,

wherein a distance between the third node and the particular location in the first direction is greater than a distance between the first node and the particular location in the first direction,

wherein a distance between the fourth node and the particular location in the second direction is greater than a distance between the second node and the particular location in the second direction.

2. The IC of claim 1,

wherein the set of nested direct offset connections is a first set of nested direct offset connections,

wherein the direct offset connections in the first set are repeated across the node array to define a plurality of other sets of nested direct offset connections.

3. The IC of claim 1, wherein the first node and the third node are adjacent to each other without intervening nodes and the second node and the fourth node are adjacent to each other without intervening nodes.

4. The IC of claim 1, wherein the array is centered at the particular location.

5. The IC of claim 1, wherein the first direction is perpendicular to the second direction.

6. The IC of claim 1, wherein each particular nested direct offset connection between a pair of configurable nodes is at a greater distance from the particular location than the distance of all nested direct offset connections that are interior to that particular nested direct offset connection.

7. The IC of claim 1, wherein each direct offset connection is defined by a set of wire segments.

8. The IC of claim 7, wherein the set of wire segments of a particular direct offset connection comprises two different segments that are connected by a via.

9. The IC of claim 7, wherein at least one set of wire segments includes at least two wire segments on at least two different wiring layers of the IC.

10. The IC of claim 7, wherein the set of wire segments of a particular direct offset connection comprises a first subset of wire segments arranged in a Manhattan direction and a second subset of wire segments arranged in a non-Manhattan direction.

11. An electronic device comprising:

an integrated circuit (“

IC”

) comprising;

a plurality of configurable nodes arranged in an array having a plurality of rows and a plurality of columns, the plurality of configurable nodes comprising a first group of configurable nodes aligned along a particular direction and a second group of configurable nodes aligned along a different direction; and

a set of direct offset turn connections arranged across the node array in a repetitive nested architecture, each direct offset turn connection connecting a node from the first group of configurable nodes to a node from the second group of configurable nodes,

wherein each direct offset turn connection comprises at least two wire segments that are arranged in at least two different directions and intersect to define a turn,

wherein no direct offset turn connection overlaps with another direct offset turn connection.

12. The electronic device of claim 11, wherein the set of direct offset turn connections are symmetrically arranged across the node array.

13. The electronic device of claim 11, wherein at least one direct offset turn connection further comprises a buffer circuit.

14. The electronic device of claim 11, wherein the nodes are configurable interconnect circuits.

15. The electronic device of claim 11, wherein the nodes are switchboxes.

16. The electronic device of claim 11, wherein the set of direct offset turn connections comprises a particular connection between a first node from the first group and a second node from the second group, the first and second nodes separated by at least one of two rows and two columns in the node array.

17. The electronic device of claim 11, wherein the set of direct offset turn connections comprises Manhattan and non-Manhattan connections, wherein for at least one Manhattan connection, a first wire segment of the two wire segments is arranged vertically and a second wire segment of the two wire segments is arranged horizontally.

18. The electronic device of claim 11, wherein the two wire segments of a particular direct offset turn connection comprise a first wire segment arranged in a Manhattan direction and a second wire segment arranged in a non-Manhattan direction.

19. The electronic device of claim 11, wherein a first wire segment of the two wire segments of a particular direct offset turn connection is on a first wiring layer of the IC and a second wire segment of the particular direct offset turn connection is on a second different wiring layer of the IC.

20. The electronic device of claim 11, wherein the two wire segments of a particular direct offset turn connection are connected by a via.