PLL circuit

• US 8,415,998 B2
• Filed: 09/23/2011
• Issued: 04/09/2013
• Est. Priority Date: 12/15/2010
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Tabata, Mitsushi
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/241,549
• Publication Number:
  US 20120154000A1
• Time in Patent Office: 564 Days
• Field of Search: 327/147, 327/156
• US Class Current: 327/156
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence

Abstract

A PLL circuit, has a phase comparator for comparing phases of a reference clock and a feedback clock, and outputting a phase comparison signal indicating the phase difference; a charge pump circuit, which, during a time period corresponding to the phase difference, outputs a first charge pump current and a second charge pump current; a loop filter, having a capacitor storing electric charge based on the first and second charge pump currents, which generates a control voltage due to stored electric charge; an oscillator generating an output clock at a frequency according to the control voltage; a frequency divider frequency-dividing the output clock and outputs the feedback clock; and a charge pump adjustment circuit, which, when in a locked state, adjusts current quantity of the first or the second charge pump current such that the phase difference is suppressed, according to the phase difference indicated by the phase comparison signal.

Claims

1. A PLL circuit, comprising:

a phase comparator configured to compare phases of a reference clock and a feedback clock, and output a phase comparison signal indicating a difference between the phases;

a charge pump circuit configured to, during a time period corresponding to the difference in phases indicated by the phase comparison signal, output a first charge pump current and a second charge pump current, generate the first charge pump current over a longer time period than the second charge pump current when the phase difference indicated by the phase comparison signal is positive, and generate the first charge pump current over a shorter time period than the second charge pump current when the phase difference is negative;

a loop filter including a capacitor storing electric charge based on the first and second charge pump currents, and configured to generate a control voltage due to stored electric charge, one of the first and second charge pump currents being a charging current which charges the capacitor; and

the other one of the first and second charge pump currents being a discharging current which discharges the capacitor;

an oscillator configured to generate an output clock at a frequency according to the control voltage;

a frequency divider configured to frequency-divide the output clock and output the feedback clock; and

a charge pump adjustment circuit configured to, when in a locked state, adjust current quantity of the first or the second charge pump current such that the difference in current values of the first and second charge pump currents is suppressed and the phase difference is suppressed, according to the phase difference indicated by the phase comparison signal.

2. The PLL circuit according to claim 1, wherein, when in an unlocked state, the charge pump adjustment circuit does not adjust the current value of the first or the second charge pump current.

3. The PLL circuit according to claim 1, wherein

the charge pump circuit includes a first current generation circuit which generates the first charge pump current, and a second current generation circuit which generates the second charge pump current;

the first current generation circuit generates the first charge pump current during a time period according to the phase difference indicated by the phase comparison signal, and adjusts the current value of the first charge pump current according to the first current adjustment signal output by the charge pump adjustment circuit; and

the second current generation circuit generates the second charge pump current during a time period according to the phase difference indicated by the phase comparison signal, and adjusts the current value of the second charge pump current according to the second current adjustment signal output by the charge pump adjustment circuit.

4. The PLL circuit according to claim 3, wherein

the first current generation circuit includes a plurality of first current generation units provided in parallel between a first voltage and an output terminal, and a number of first current generation units according to the first current adjustment signal generate the first charge pump current during a time period according to the phase difference indicated by the phase comparison signal;

and

the second current generation circuit includes a plurality of second current generation units provided in parallel between a second voltage and an output terminal, and a number of second current generation units according to the second current adjustment signal generate the second charge pump current during a time period according to the phase difference indicated by the phase comparison signal.

5. The PLL circuit according to claim 4, wherein

the first current generation unit includes a first transistor which is controlled to be conducting or non-conducting according to the phase comparison signal, a second transistor which is controlled to be conducting or non-conducting according to the first current adjustment signal, and a third transistor which generates a prescribed current, and the first, second and third transistors are connected in series between the first voltage and output terminal;

and

the second current generation unit includes a fourth transistor which is controlled to be conducting or non-conducting according to the phase comparison signal, a fifth transistor which is controlled to be conducting or non-conducting according to the second current adjustment signal, and a sixth transistor which generates a prescribed current, and the fourth, fifth and sixth transistors are connected in series between the second voltage and output terminal.

6. The PLL circuit according to claim 3, wherein

the first current generation circuit includes, between a first voltage and an output terminal, a first transistor and first current source transistor, the first current source transistor generates a current according to the first current adjustment signal, and the first transistor outputs the current of the first current source transistor to the output terminal as the first charge pump current during a time period according to the phase difference indicated by the phase comparison signal;

and

the second current generation circuit includes, between a second voltage and an output terminal, a second transistor and second current source transistor, the second current source transistor generates a current according to the second current adjustment signal, and the second transistor outputs the current of the second current source transistor to the output terminal as the second charge pump current during a time period according to the phase difference indicated by the phase comparison signal.

7. The PLL circuit according to claim 6, wherein

the first current generation circuit further includes the first current source transistor and a plurality of first current mirror transistors forming a first current mirror circuit, and a first current mirror current flows in a number of first current mirror transistors according to the first current adjustment signal;

and

the second current generation circuit further includes the second current source transistor and a plurality of second current mirror transistors forming a second current mirror circuit, and a second current mirror current flows in a number of second current mirror transistors according to the second current adjustment signal.

8. A method of adjustment of a PLL circuit including a phase comparator configured to compare phases of a reference clock and feedback clock and output a phase comparison signal indicating a difference between the phases, a charge pump circuit configured to output a first charge pump current and second charge pump current during a time period according to the difference in phases indicated by the phase comparison signal, generate the first charge pump current over a longer time period than the second charge pump current when the phase difference indicated by the phase comparison signal is positive, and generate the first charge pump current over a shorter time period than the second charge pump current when the phase difference is negative, a loop filter including a capacitor which stores electric charge based on the first and second charge pump currents and configured to generate a control voltage due to stored electric charge, one of the first and second charge pump currents being a charging current which charges the capacitor;

and the other one of the first and second charge pump currents being a discharging current which discharges the capacitor, an oscillator configured to generate an output clock at a frequency according to the control voltage, and a frequency divider configured to frequency-divide the output clock and output the feedback clock, the method comprising;

adjusting, when in a locked state, a current value of the first or second charge pump current such that the difference in current values of the first and second charge pump currents is suppressed and the phase difference is suppressed, according to the difference in phases indicated by the phase comparison signal.