Differential plate line screen test for ferroelectric latch circuits

• US 8,416,598 B2
• Filed: 05/17/2010
• Issued: 04/09/2013
• Est. Priority Date: 05/21/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Summerfelt, Scott R., Rodriguez, John Anthony, McAdams, Hugh P., Bartling, Steven Craig
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US12/781,601
• Publication Number:
  US 20100296329A1
• Time in Patent Office: 1,058 Days
• Field of Search: 365/49.13, 365/65, 365/109, 365/117, 365/145, 257/295, 257/E21.208, 257/E21.663, 257/E21.664, 257/E27.104, 257/E29.164
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

Claims

1. An integrated circuit, comprising:

at least one latch circuit comprising;

cross-coupled inverters driving first and second storage nodes;

a first ferroelectric capacitor having a first plate coupled to the first storage node and a second plate; and

a second ferroelectric capacitor having a first plate coupled to the second storage node and a second plate;

input circuitry for setting the state of the at least one latch circuit;

output circuitry for sensing the state of the at least one latch circuit;

a first plate line coupled to the second plate of the first ferroelectric capacitor;

a second plate line coupled to the second plate of the second ferroelectric capacitor; and

plate line driver circuitry for applying low and high bias voltages to each of the second plates of the first and second ferroelectric capacitors to polarize the first and second ferroelectric capacitors to opposite polarization states, corresponding to the state of the latch circuit, and for biasing, in a test operation, a first bias voltage to the second plate of the first ferroelectric capacitor and a second bias voltage to the second plate of the second ferroelectric capacitor, the second bias voltage lower than the first bias voltage by a selected differential.

2. The integrated circuit of claim 1, wherein the at least one latch circuit further comprises:

a third ferroelectric capacitor having a first plate coupled to the first storage node and a second plate coupled to a second plate line; and

a fourth ferroelectric capacitor having a first plate coupled to the second storage node and a second plate coupled to the second plate line;

and wherein the plate line driver circuitry is also for applying low and high bias voltages to the second plate line to polarize the third and fourth ferroelectric capacitors, and is also for biasing, in the test operation, the second plate line to a ground voltage.

3. The integrated circuit of claim 1, wherein the latch circuit corresponds to a static random access memory cell, the memory cell further comprising first and second pass gates having a conduction path coupled between the first and second storage nodes and first and second complementary bit lines, respectively, and having a control terminal receiving a word line;

and further comprising;

word line drivers for selectively turning the first and second pass gates on and off;

read/write circuitry, coupled to the first and second bit lines.

4. The integrated circuit of claim 1, wherein the latch circuit corresponds to a flip-flop in a logic circuit.