Transmission gate-based spin-transfer torque memory unit

• US 8,416,615 B2
• Filed: 05/18/2012
• Issued: 04/09/2013
• Est. Priority Date: 07/10/2008
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Chen, Yiran, Li, Hai, Liu, Hongyue, Lu, Yong, Li, Yang
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US13/474,839
• Publication Number:
  US 20120230093A1
• Time in Patent Office: 326 Days
• Field of Search: 365/48, 365/55, 365/62, 365/66, 365/74, 365/78, 365 80- 93, 365/100, 365/130, 365/131, 365/148, 365/158, 365171-173, 365/209, 365/213, 365/225.5, 365/230.07, 365/232, 365/243.5, 216/22, 257/421, 257/E21.665, 438/3, 428810-816, 428817-8251, 428/826, 977933-935
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: Y10S 977/935 Spin dependent tunnel, SDT, junction, e.g. tunneling magnetoresistance, TMR

Abstract

A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

Claims

1. A memory unit comprising:

a magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and

a NMOS transistor in parallel electrical connection with a PMOS transistor, the NMOS transistor and the PMOS transistor electrically connected with the magnetic tunnel junction data cell, the NMOS transistor and the PMOS transistor are separately addressable.

2. A memory unit according to claim 1, wherein the NMOS transistor comprises a NMOS gate electrode electrically coupled to a first word line, and the PMOS transistor comprises a PMOS gate electrode electrically coupled to a second word line and the first word line is separately addressable from the second word line.

3. A memory unit according to claim 1, wherein the spin-transfer torque memory unit has a symmetric driving ability for a first write current and an opposing second write current.

4. A memory unit according to claim 3, wherein the spin-transfer torque memory unit has a symmetric driving ability for the first write current and the second write current when a voltage of 1.5V or less is applied across the spin-transfer torque memory unit.

5. A memory unit according to claim 1, wherein the PMOS transistor is body biased.

6. A memory unit according to claim 1, wherein the NMOS transistor comprises a NMOS gate electrode having a gate length value of 0.13 micrometer or less.

7. A memory unit according to claim 1, wherein the NMOS transistor comprises a NMOS gate electrode having a gate length value in a range from 0.032 micrometer to 0.10 micrometer and the spin-transfer torque memory unit has a symmetric driving ability for the first write current of 1.5V or less and the second write current of −

1.5V or less.

8. A spin-transfer torque memory unit comprising:

a magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and

a transmission gate electrically coupled to the magnetic tunnel junction data cell, the transmission gate comprising;

a NMOS transistor in parallel electrical connection with a PMOS transistor.

9. A spin-transfer torque memory unit according to claim 8, wherein the NMOS transistor comprises a NMOS gate electrode electrically coupled to a first word line, and the PMOS transistor comprises a PMOS gate electrode electrically coupled to a second word line and the first word line is separately addressable from the second word line.

10. A spin-transfer torque memory unit according to claim 8, wherein the spin-transfer torque memory unit has a symmetric driving ability for a first write current and an opposing second write current.

11. A spin-transfer torque memory unit according to claim 10, wherein the spin-transfer torque memory unit has a symmetric driving ability for the first write current and the second write current when a voltage of 1.5V or less is applied across the spin-transfer torque memory unit.

12. A spin-transfer torque memory unit according to claim 8, wherein the PMOS transistor is body biased.

13. A spin-transfer torque memory unit according to claim 8, wherein the NMOS transistor comprises a NMOS gate electrode having a gate length value of 0.13 micrometer or less.

14. A spin-transfer torque memory unit according to claim 13, wherein spin-transfer torque memory unit has a symmetric driving ability for the first write current of 1.5V or less and the second write current of −

1.5V or less.

15. A spin-transfer torque memory unit comprising:

a magnetic tunnel junction data cell comprising a ferromagnetic free layer and a ferromagnetic reference layer separated by a oxide barrier layer, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and

a transmission gate electrically between the source line and the magnetic tunnel junction data cell, the transmission gate comprising;

a NMOS transistor in parallel electrical connection with a PMOS transistor;

a first word line is electrically coupled to the NMOS transistor; and

a second word line is electrically coupled to the PMOS transistor, the second word line being electrically isolated from the first word line;

wherein, the spin-transfer torque memory unit is configured so that a first write current in a first direction flows through the PMOS transistor and not the NMOS transistor and a second write current in a second direction flows through the NMOS transistor and not the PMOS transistor.

16. A spin-transfer torque memory unit according to claim 15, wherein the spin-transfer torque memory unit has a symmetric driving ability for the first write current and the second write current.

17. A spin-transfer torque memory unit according to claim 15, wherein the spin-transfer torque memory unit has a symmetric driving ability for the first write current and the second write current when a voltage of 1.5V or less is applied across the spin-transfer torque memory unit.

18. A spin-transfer torque memory unit according to claim 15, wherein the PMOS transistor is body biased.

19. A spin-transfer torque memory unit according to claim 15, wherein the NMOS transistor comprises a NMOS gate electrode having a gate length value of 0.13 micrometer or less.

20. A spin-transfer torque memory unit according to claim 19, wherein spin-transfer torque memory unit has a symmetric driving ability for the first write current of 1.5V or less and the second write current of −

1.5V or less.