Erase and programming techniques to reduce the widening of state distributions in non-volatile memories
First Claim
1. A method of operating a non-volatile memory array comprising one or more erase blocks each having a plurality on memory cells formed along bitlines and wordlines, the method comprising:
- performing an erase operation on the memory cells of one or more selected erase blocks, the erase operation including;
performing a stress phase, including;
applying a pattern of voltage levels to the bitlines corresponding to the selected erase blocks, where the pattern includes a voltage differential between at least one pair of adjacent ones of the corresponding bit lines; and
while applying the pattern of voltage levels to the bitlines, applying a pulse of positive voltage to one or more of the wordlines corresponding to the selected erase blocks; and
performing an erase phase, including biasing the selected erase blocks to induce erasure of the memory cells thereof.
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Abstract
Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.
113 Citations
40 Claims
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1. A method of operating a non-volatile memory array comprising one or more erase blocks each having a plurality on memory cells formed along bitlines and wordlines, the method comprising:
performing an erase operation on the memory cells of one or more selected erase blocks, the erase operation including; performing a stress phase, including; applying a pattern of voltage levels to the bitlines corresponding to the selected erase blocks, where the pattern includes a voltage differential between at least one pair of adjacent ones of the corresponding bit lines; and while applying the pattern of voltage levels to the bitlines, applying a pulse of positive voltage to one or more of the wordlines corresponding to the selected erase blocks; and performing an erase phase, including biasing the selected erase blocks to induce erasure of the memory cells thereof. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of operating a non-volatile memory array of one or more erase blocks each having a plurality of memory cells formed along bitlines and wordlines, where the array is of a NAND type of architecture where a plurality of memory cells are connected in series between first and second select gates, the method comprising:
performing an erase operation on the memory cells of one or more selected erase blocks, the erase operation including; performing a stress phase, including applying a first high voltage pulse to a first subset of one or more non-adjacent ones of the wordlines corresponding to the selected erase blocks, the first subset including at least one wordline corresponding to memory cells not adjacent to a select gate; and while applying the high voltage pulse to the first subset of wordlines, setting the others of the wordlines corresponding to the selected erase blocks to a low voltage level; and performing an erase phase, including biasing the selected erase blocks to induce erasure of the memory cells thereof. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A method of writing data to a non-volatile memory, comprising:
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performing an alternating series of program and verify phases on a selected plurality of memory cells formed along a selected wordline, wherein the verify phase includes performing a verify operation that individually locks out from further programming selected memory cells in response to successfully verifying as programmed to a corresponding target state, and wherein the programming phase includes applying a first and a second programming pulse to the selected wordline without an intervening verify operation, wherein a non-selected wordline adjacent to the selected wordline is set to a first voltage during the first programming pulse and to a second voltage during the second voltage during the second programming pulse, wherein the first and second voltages are distinct positive voltages. - View Dependent Claims (36, 37, 38, 39, 40)
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Specification