Techniques for controlling a semiconductor memory device

• US 8,416,636 B2
• Filed: 12/29/2010
• Issued: 04/09/2013
• Est. Priority Date: 02/12/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Carman, Eric S., Bauser, Philippe Bruno, Daga, Jean-Michel
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US12/980,766
• Publication Number:
  US 20110199848A1
• Time in Patent Office: 832 Days
• Field of Search: None
• US Class Current: 365/205
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns. Applying the plurality of voltage potentials to the plurality of memory cells may include applying a first voltage potential to a first memory cell in a row of the array via a first respective bit line and a first switch transistor, applying a second voltage potential to a second memory cell in the row of the array via a second respective bit line and a second switch transistor, and applying a third voltage potential to at least one third memory cell in the row of the array via at least one third respective bit line and at least one third switch transistor, wherein the at least one third memory cell may be located between the first memory cell and the second memory cell in the row of the array.

Claims

1. A method for controlling a semiconductor memory device comprising:

applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns, wherein applying the plurality of voltage potentials to the plurality of memory cells comprises;

applying a first voltage potential to a first memory cell in a row of the array via a first respective bit line and a first switch transistor;

applying a second voltage potential to a second memory cell in the row of the array via a second respective bit line and a second switch transistor; and

applying a third voltage potential to at least one third memory cell in the row of the array via at least one third respective bit line and at least one third switch transistor, wherein the at least one third memory cell is located between the first memory cell and the second memory cell in the row of the array; and

wherein the at least one third memory cell comprises;

a first region coupled to a respective source line of the array;

a second region coupled to the at least one third respective bit line of the array;

a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region is electrically floating and disposed between the first region and the second region.

2. The method according to claim 1, wherein the first switch transistor couples the first memory cell to first data sense amplifier circuitry.

3. The method according to claim 2, wherein the second switch transistor couples the second memory cell to second data sense amplifier circuitry.

4. The method according to claim 3, wherein the at least one third switch transistor couples the at least one third memory cell to the first data sense amplifier circuitry or the second data sense amplifier circuitry.

5. The method according to claim 4, wherein the first voltage potential, the second voltage potential, and the third voltage potential are simultaneously applied by the first data sense amplifier circuitry or the second data sense amplifier circuitry.

6. The method according to claim 5, wherein the first voltage potential, the second voltage potential, and the third voltage potential are equal.

7. The method according to claim 6, wherein the first voltage potential, the second voltage potential, and the third voltage potential are equal to a masking operation voltage potential.

8. The method according to claim 1, wherein the first voltage potential is applied by first data sense amplifier circuitry to determine a data state stored in the first memory cell.

9. The method according to claim 8, wherein the second voltage potential is applied by second data sense amplifier circuitry to determine a data state stored in the second memory cell.

10. The method according to claim 9, wherein the third voltage potential is applied by the first data sense amplifier circuitry or the second data sense amplifier circuitry to mask the at least one third memory cell from disturbance.

11. The method according to claim 10, wherein the third voltage potential is applied to at least two of the at least one third memory cell in the row of the array via at least two of the at least one third respective bit line.

12. The method according to claim 9, wherein the at least one third respective bit line is electrically floating after the application of the third voltage potential.

13. The method according to claim 12, wherein the third voltage potential is maintained via at least one respective driver transistor.

14. A semiconductor memory device comprising:

a plurality of memory cells arranged in an array of rows and columns, at least one of the plurality of memory cells comprising;

a first region coupled to a respective source line of the array;

a second region coupled to a respective bit line of the array, wherein the respective bit line of the array is coupled to data sense amplifier circuitry via a switch transistor;

a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region is electrically floating and disposed between the first region and the second region; and

a third region coupled to a respective carrier injection line of the array, wherein the third region is disposed adjacent to the first region or the second region.

15. The semiconductor memory device according to claim 14, wherein the respective bit line is one of a plurality of bit lines in the array that are coupled to the data sense amplifier circuitry.

16. The semiconductor memory device according to claim 14, wherein the data sense amplifier circuitry is one of a plurality of data sense amplifier circuits in the array.

17. The semiconductor memory device according to claim 16, wherein at least some of the plurality of data sense amplifier circuits are configured on opposite sides of the array.

18. The semiconductor memory device according to claim 16, wherein at least some of the plurality of data sense amplifier circuits are alternatively coupled to the plurality of memory cells of the array.

19. The semiconductor memory device according to claim 18, wherein at least some of the plurality of data sense amplifier circuits are alternatively coupled to a pair of memory cells in the row of the array.

20. The semiconductor memory device according to claim 14, wherein at least some of the plurality of data sense amplifier circuits are alternatively coupled to a single memory cell in the row of the array.

21. The semiconductor memory device according to claim 14, wherein the switch transistor is one of a plurality of switch transistors in the array that are coupled to the data sense amplifier circuitry.

22. The semiconductor memory device according to claim 14, further comprising a driver transistor coupling the respective bit line of the array to a power source.

23. The semiconductor memory device according to claim 22, wherein the driver transistor is one of a plurality of driver transistors in the array.