Receive beamformer for ultrasound having delay value sorting

• US 8,416,643 B2
• Filed: 03/18/2010
• Issued: 04/09/2013
• Est. Priority Date: 03/24/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Magee, David Patrick
• Primary Examiner(s): Alsomiri, Isam
• Assistant Examiner(s): HULKA, JAMES R
• Application Number:
  US12/726,514
• Publication Number:
  US 20100249596A1
• Time in Patent Office: 1,118 Days
• Field of Search: 367/138, 600/447
• US Class Current: 367/138
• CPC Class Codes: G10K 11/346 using phase variation

Abstract

A method of processing ultrasound signals received from a plurality of data channels each associated with a transducer element. A sorted delay data table having sorted delay data is generated that includes a channel identifier, a fractional delay value, and integer delay value. The sorted delay data table clusters together channel groups including a first channel group having data channels with the first fractional delay value and a second channel group with data channels with the second fractional delay value. Control signals are generated based on the sorted delay data that implements data path combining by directing channel data from the first channel group for processing by a first interpolation filter that provides the first fractional delay value and channel data associated with the second channel group for processing by a second interpolation filter that provides the second fractional delay value. Summing signals output by the first and second interpolation filter forms the ultrasound beamformed signal.

Claims

1. A method of processing ultrasound signals received from a plurality of data channels each associated with different transducer elements, said data channels each having a channel identifier corresponding to a particular one of said transducer elements, a fractional delay value of each channel, and an integer delay value, comprising:

generating a sorted delay data table having sorted delay data by sorting delay data that includes said channel identifier, said fractional delay value, and said integer delay value, wherein said fractional delay value includes a plurality of different fractional delay values including at least a first and a second fractional delay value, said sorted delay table data clustering together channel groups comprising a first channel group including said data channels that have said first fractional delay value and a second channel group that includes said data channels that have said second fractional delay value;

generating control signals based on the sorted delay data that implements data path combining by directing channel data from said first channel group for processing the control signals by a first interpolation filter that provides said first fractional delay value and channel data associated with said second channel group for processing by a second interpolation filter that provides said second fractional delay value, and

summing signals output by said first and said second interpolation filter to form a beamformed signal,

wherein said plurality of different fractional delay values are given by integer*Tres, wherein Tres is a timing resolution (Tres) for said ultrasound receive beamformed signal and said integer corresponds to integer values from zero to ceil(Ts/Tres)−

1, where Ts is a sampling period for digitizing said channel data, wherein ceil (Ts/Tres) is a determination of the greater of Ts or Tres,

wherein said beamformed signal at a time sample n for a scan line is calculated using;

2. The method of claim 1, wherein said first interpolation filter and said second interpolation filter are part of a single shared interpolation filter bank consisting of said first interpolation filter, said second interpolation filter, and a plurality of other interpolation filters, and

wherein said plurality of other interpolation filters each provide a fractional delay value different from one another and different from said first and said second fractional delay value.

3. The method of claim 1, wherein said different transducer elements comprise piezoelectric transducers.

4. The method of claim 1, wherein said generating said sorted delay data table, said generating said control signals, said interpolation filtering and said summing are performed by at least one digital signal processor (DSP) integrated circuit (IC).

5. An ultrasound diagnostic imaging system, comprising:

a plurality of transducer elements for transmitting ultrasound transmit pulses toward a target tissue region, and receiving echo signals from said target tissue region in response to said transmit pulses;

a transmit section for driving said plurality of transducer elements for said transmitting of said ultrasound transmit pulses, and

a receive section for processing a plurality of sensing signals generated by said plurality of transducers responsive to said echo signals, said receive section defining a plurality of data channels each associated with different one of said plurality of transducer elements, said receive section comprising;

digitizing blocks, integer delaying blocks and apodizing blocks for processing said sensing signals in each of said plurality of data channels;

data path combining circuitry for generating a plurality of data combinations by combining channel data from two or more of said plurality of data channels, said channel data including a channel identifier, a fractional delay value, and an integer delay value;

a shared interpolation filter bank comprising a plurality of interpolation filters comprising a first interpolation filter that provides a first fractional delay value and a second interpolation filter that provides a second fractional delay value coupled to an output of said data path combining circuitry for interpolation filtering said plurality of data combinations;

a controller and associated memory, wherein said controller (i) generates a sorted delay data table having sorted delay data by sorting said channel data, said sorted delay data table clustering together channel groups so that a first channel group includes said data channels that have said first fractional delay value and a second channel group that includes said data channels that have said second fractional delay value, and (ii) generates control signals based on said sorted delay data that are coupled to said data path combining circuitry for by directing said channel data from said first channel group for processing by said first interpolation filter and said channel data associated with said second channel group for processing by said second interpolation filter;

a summer for summing coupled to outputs of said single shared interpolation filter bank to form a beamformed signal;

a backend imaging display processor coupled to receive and process said beamformed signal to generate a display signal, said display signal being suitable for causing display devices to produce an image, and

a display device for receiving said display signal and producing said image,

wherein said data combinations are selected from the group consisting of;

only Channel ID;

fractional delay values; and

integer delay values,

wherein said plurality of interpolation filters each provide a different one of said fractional delay values

wherein said different fractional delay values are based on integer*Tres, wherein Tres is a timing resolution (Tres) for said beamformed signal and said integer corresponds to integer values from zero to ceil(Ts/Tres)−

1, where Ts is a sampling period for said digitizing, wherein ceil (Ts/Tres) is a determination of the greater of Ts or Tres,

wherein said beamformed signal at a time sample n for a scan line is calculated using;

6. The system of claim 5, wherein said data path combining circuitry is implemented by a switching circuit that receives said control signals.

7. The system of claim 5, wherein at least one digital signal processor (DSP) integrated circuit (“

IC”

) provides said integer delaying, said apodizing blocks, said data path combining circuitry, said shared interpolation filter bank, said controller and associated memory, and said summer.

8. A digital signal processor (DSP) integrated circuit (IC) for ultrasound signal processing, comprising:

a substrate having a semiconductor surface;

integer delaying blocks and apodizing blocks for processing sensing signals in each of a plurality of data channels;

data path combining circuitry for generating a plurality of data combinations by combining channel data from two or more of said plurality of data channels, said channel data including a channel identifier, a fractional delay value, and an integer delay value;

a shared interpolation filter bank comprising a plurality of interpolation filters comprising a first interpolation filter that provides a first fractional delay value and a second interpolation filter that provides a second fractional delay value coupled to an output of said data path combining circuitry for interpolation filtering said plurality of data combinations;

a controller and associated memory, wherein said controller (i) generates a sorted delay data table having sorted delay data by sorting said channel data, said sorted delay data table clustering together channel groups so that a first channel group includes said data channels that have said first fractional delay value and a second channel group that includes said data channels that have said second fractional delay value, and (ii) generates control signals based on said sorted delay data that are coupled to said data path combining circuitry for by directing said channel data from said first channel group for processing by said first interpolation filter and said channel data associated with said second channel group for processing by said second interpolation filter, and

a summer for summing coupled to outputs of said single shared interpolation filter bank to form a beamformed signal

wherein said different fractional delay values are based on integer*Tres, wherein Tres is a timing resolution (Tres) for said beamformed signal and said integer corresponds to integer values from zero to ceil(Ts/Tres)−

1, where Ts is a sampling period for digitizing, wherein ceil (Ts/Tres) is a determination of the greater of Ts or Tres,

wherein said beamformed signal at a time sample n for a scan line is calculated using;

9. The DSP IC of claim 8, wherein said plurality of interpolation filters each provide a different one of said fractional delay values.

10. The DSP IC of claim 8, wherein said data path combining circuitry is implemented by a switching circuit that receives said control signals.