Signal edge detection circuitry and methods

• US 8,416,903 B1
• Filed: 04/29/2011
• Issued: 04/09/2013
• Est. Priority Date: 11/26/2003
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Oh, John, Tam, Samson, Wortman, Curt, Berube, Jean Luc
• Primary Examiner(s): Washburn, Daniel
• Assistant Examiner(s): Ghulamali, Qutbuddin
• Application Number:
  US13/097,252
• Time in Patent Office: 711 Days
• Field of Search: 375/355, 375/358, 375/360, 375/366, 375/367
• US Class Current: 375/355
• CPC Class Codes: H03K 5/1534 Transition or edge detectors
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

Double data rate (“DDR”) circuitry or the like is modified or enhanced to include edge detection capability. During edge detection mode the circuitry is supplied with serial training data that includes successive pairs of equal-valued bits. Several, differently-phased, candidate clock signals are used one after another in order of increasing phase to clock the DDR circuitry. Adjacent bits in the training data that should be equal-valued are captured by the DDR circuitry and compared. Any candidate clock signal that causes the bits thus compared to be unequal is flagged as having phase close to edges in the data. The approximate phase of data edges is thereby indicated by the phase (or phases) of the candidate clock signal (or signals) causing the bits compared as described above to be unequal.

Claims

1. A method comprising:

sampling a data signal with a clock signal, wherein first and second consecutive samples in each consecutive pair of samples of the sampled data signal have a same logic value;

adjusting the clock signal used to sample the data signal by each one of a predetermined plurality of phase offsets;

determining whether the first and second consecutive samples in at least one of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal have different logic values,

wherein the data signal is grouped into consecutive pair of samples that remain unaltered during the adjusting of the clock signal; and

selecting one of the predetermined plurality of phase offsets based on the determining performed for each one of the predetermined plurality of phase offsets.

2. The method defined in claim 1, wherein:

the sampling of the data signal is continuous during the adjusting of the clock signal, and

grouping of the data signal into consecutive pairs of samples remains unaltered during the adjusting of the clock signal.

3. The method defined in claim 1, wherein a phase difference between each of the plurality of phase offsets and a phase-adjacent preceding one of the plurality is positive and less than a duration of a bit in the data signal.

4. The method defined in claim 3, wherein a sum of the phase differences between each of the plurality of phase offsets and the phase-adjacent preceding one of the plurality is at least equal to a duration of a bit in the data signal.

5. The method defined in claim 1, further comprising:

in response to determining that the first and second consecutive samples in the at least one of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal have different logic values; and

adjusting the sampling of the data signal sampled with the adjusted clock signal, wherein the first and second consecutive samples in the at least one of each said consecutive pair of samples of the data signal have a same logic value.

6. The method defined in claim 1, further comprising:

causing the data signal to conform to a predetermined training data pattern during the sampling, adjusting, and determining; and

after the selecting, causing the data signal to represent data that is not predetermined.

7. The method defined in claim 1, wherein:

the data signal conforms to a predetermined training data pattern, and

for every group of adjacent data bits within the predetermined training data pattern which have a same logic value, the number of adjacent bits in the group is even.

8. The method defined in claim 1, wherein the selecting comprises:

selecting one of the plurality of the phase offsets for which it is determined that the first and second consecutive samples of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal have a same logic value.

9. The method defined in claim 1, further comprising:

for each of the plurality of phase offsets, determining a count of the number of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal where the first and second consecutive samples of each said consecutive pair of samples have different logic values; and

selecting one of the plurality of the phase offsets based at least in part on the count for each of the plurality of phase offsets.

10. A circuit comprising:

a circuitry configured to;

sample a data signal with a clock signal, wherein first and second consecutive samples in each consecutive pair of samples of the sampled data signal have a same logic value;

adjust the clock signal used to sample the data signal by each one of a predetermined plurality of phase offsets; and

determine whether the first and second consecutive samples in at least one of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal have different logic values,

wherein the data signal is grouped into said each consecutive pair of samples that remains unaltered during the adjusting of the clock signal; and

the circuitry further configured to select one of the predetermined plurality of phase offsets based on the determining performed for each one of the predetermined plurality of phase offsets.

11. The circuit defined in claim 10, wherein:

the sampling of the data signal is continuous during the adjusting of the clock signal, and

grouping of the data signal into consecutive pairs of samples remains unaltered during the adjusting of the clock signal.

12. The circuit defined in claim 11, further comprising circuitry configured to:

cause the data signal to conform to a predetermined training data pattern during the sampling, adjusting, and determining; and

after the selecting, cause the data signal to represent data that is not predetermined.

13. The circuit defined in claim 10, wherein a phase difference between each of the plurality of phase offsets and a phase-adjacent preceding one of the plurality is positive and less than a duration of a bit in the data signal.

14. The circuit defined in claim 13, wherein a sum of the phase differences between each of the plurality of phase offsets and the phase-adjacent preceding one of the plurality is at least equal to a duration of a bit in the data signal.

15. The circuit defined in claim 10, further comprising circuitry configured to:

in response to determining that the first and second consecutive samples in the at least one of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal have different logic values; and

adjust the sampling of the data signal sampled with the adjusted clock signal, wherein the first and second consecutive samples in the at least one of each said consecutive pair of samples of the data signal have a same logic value.

16. The circuit defined in claim 10, wherein:

the data signal conforms to a predetermined training data pattern, and

for every group of adjacent data bits within the predetermined training data pattern which have a same logic value, the number of adjacent bits in the group is even.

17. The circuit defined in claim 10, wherein the circuitry configured to select is further configured to:

select one of the plurality of the phase offsets for which it is determined that the first and second consecutive samples of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal have a same logic value.

18. The circuit defined in claim 10, further comprising:

circuitry configured to, for each of the plurality of phase offsets, determine a count of the number of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal where the first and second consecutive samples of each said consecutive pair of samples have different logic values;

wherein;

the circuitry configured to select is further configured to select one of the plurality of the phase offsets based at least in part on the count for each of the plurality of phase offsets.

19. A circuit comprising:

a circuitry configured to;

sample a data signal with a clock signal, wherein first and second consecutive samples in each consecutive pair of samples of the sampled data signal have a same logic value;

adjust the clock signal used to sample the data signal by each one of a predetermined plurality of phase offsets, wherein;

the sampling of the data signal is continuous during the adjusting of the clock signal, and

grouping of the data signal into each of the consecutive pair of samples remains unaltered during the adjusting of the clock signal; and

determine whether the first and second consecutive samples in at least one of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal have different logic values; and

the circuitry further configured to select one of the predetermined plurality of the phase offsets for which it is determined that the first and second consecutive samples of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal have the same logic value.

20. The circuit defined in claim 19, further comprising:

circuitry configured to, for each of the plurality of phase offsets, determine a count of the number of each said consecutive pair of samples of the data signal sampled with the adjusted clock signal where the first and second consecutive samples of each said consecutive pair of samples have different logic values;

wherein;

the circuitry configured to select is further configured to select one of the plurality of the phase offsets based at least in part on the count for each of the plurality of phase offsets.