Systems and methods for electricity metering
First Claim
1. An apparatus to implement a Phased Locked Loop (PLL) comprising:
- a Voltage Controlled Oscillator (VCO);
a microprocessor;
a digital-to-analog converter (DAC); and
an analog-to-digital converter (ADC);
wherein said VCO drives a clock of said microprocessor;
wherein said microprocessor controls sampling time of said ADC at times determined by said clock of said microprocessor;
wherein said ADC monitors an input analog signal source and converts said signal to digital format;
wherein said microprocessor is in communication with said ADC and receives and filters said output digital signal from said ADC;
wherein said microprocessor controls output of said DAC based upon said filtered output digital signal from said ADC; and
wherein said DAC controls input of said VCO to close said PLL.
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Accused Products
Abstract
In one aspect, the invention comprises a system comprising: a master data clock source; one or more transponders; and a plurality of remote power line transceivers; wherein all of said plurality of transceivers are connected to a common alternating current power distribution grid; and wherein each of said plurality of transceivers has a location is operable to monitor a voltage waveform of a power line prevailing at said location. In another aspect, the invention comprises a system comprising: transponders and remote power line transceivers each connected to a common alternating current power distribution grid each operable to monitor the voltage waveform of the power line prevailing at its own location, and generate selectable frequencies from said local power line waveform of a frequency of p/q times the frequency of said power line where p and q are positive integers greater than or equal to 1.
11 Citations
3 Claims
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1. An apparatus to implement a Phased Locked Loop (PLL) comprising:
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a Voltage Controlled Oscillator (VCO); a microprocessor; a digital-to-analog converter (DAC); and an analog-to-digital converter (ADC); wherein said VCO drives a clock of said microprocessor; wherein said microprocessor controls sampling time of said ADC at times determined by said clock of said microprocessor; wherein said ADC monitors an input analog signal source and converts said signal to digital format; wherein said microprocessor is in communication with said ADC and receives and filters said output digital signal from said ADC; wherein said microprocessor controls output of said DAC based upon said filtered output digital signal from said ADC; and
wherein said DAC controls input of said VCO to close said PLL. - View Dependent Claims (2, 3)
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Specification