Apparatus, system, and method for a reconfigurable baseboard management controller

• US 8,417,774 B2
• Filed: 12/06/2007
• Issued: 04/09/2013
• Est. Priority Date: 12/06/2006
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Flynn, David, Strasser, John, Thatcher, Jonathan
• Primary Examiner(s): VOSTAL, ONDREJ C
• Application Number:
  US12/001,065
• Publication Number:
  US 20080313312A1
• Time in Patent Office: 1,951 Days
• Field of Search: 709/224, 709/221, 709/204
• US Class Current: 709/204
• CPC Class Codes: G06F 1/183 Internal mounting support structures, e.g. for printed circuit boards, internal connecting means for buses G06F13/409
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G06F 2211/002 Bus
• CPC Class Codes: G06F 2211/103 Hybrid, i.e. RAID systems with parity comprising a mix of RAID types
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/70 Details relating to dynamic memory management
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 : Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0604 : Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0608 : Saving storage space on storage systems
• CPC Class Codes: G06F 3/0613 : in relation to throughput
• CPC Class Codes: G06F 3/0619 : in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0643 : Management of files
• CPC Class Codes: G06F 3/065 : Replication mechanisms
• CPC Class Codes: G06F 3/0652 : Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 : Data buffering arrangements
• CPC Class Codes: G06F 3/0659 : Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 : Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/52 : Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/54 : Interprogram communication
• CPC Class Codes: H04L 67/02 : based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: H04L 67/1097 : for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H05K 7/1444 : Complex or three-dimensional-arrangements; Stepped or dual mother boards
• CPC Class Codes: H05K 7/1487 : Blade assemblies, e.g. blade cases or inner arrangements within a blade
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, system, and method are disclosed for a baseboard management controller (BMC) which includes an FPGA with a monitor module for monitoring the operations parameters of a host computer device. In addition, the BMC has a host connector that connects the BMC to the system bus of the host computing device, allowing the BMC access to the computing elements on the host. The host connector has reconfigurable pins with connection configuration controlled by the FPGA. In addition, the BMC has a server with a processor and associated non-volatile memory on board. The operating system provides services to the host computing device and its constituent components, as well as allowing advanced networking and interconnectivity with other BMCs in a management network.

Claims

1. A baseboard management controller module (BMC) comprising:

a reconfigurable field programmable gate array (FPGA) comprising a monitor module configured to monitor one or more operations parameters of a host computing device, the monitor module configured to be operationally independent of the host computing device;

a host connector configured to communicatively connect the BMC to a system bus of the host computing device, the system bus configured to provide connectivity between one or more computing elements of the host computing device, the host connector further comprising a plurality of functionally reconfigurable pins, wherein a connection configuration of the functionally reconfigurable pins is established by the FPGA;

a server module comprising a processor, non-volatile memory, and an operating system, the operating system configured to provide services of one or more modules to the host computing device, the server module configured to be operationally independent of the host computing device;

wherein the host connector is configured to implement a plurality of different connection configurations based on logic programming of the FPGA, a particular connection configuration of the plurality corresponding to a communication protocol used by the system bus of the host computing device;

wherein the reconfigurable FPGA is configured to establish a first connection configuration of the plurality of different connection configurations and is configured to establish a second connection configuration of the plurality of connection configurations subsequent to establishing the first connection configuration and wherein when in the first connection configuration, a block of pins of the reconfigurable FPGA are configured to communicate over a PCI express connection and when in the second connection configuration, the block of pins of the reconfigurable FPGA are configured to communicate over an Ethernet connection; and

wherein the BMC is configured to represent itself to the host computing device as a plurality of emulated computing devices, each of the emulated computing devices implemented by a different emulation module of the BMC, the emulation modules configured to share a connection to the system bus, and at least one of the emulation modules configured to represent itself as a network connection, to provide information about the network connection to the system bus, and to provide access to one or more of the emulated computing devices using the network connection such that an actual path and an emulated path of a request from the host computing device to the one or more of the emulated computing devices using the network connection are indistinguishable to the host computing device.

2. The BMC of claim 1, further comprising a network module communicatively connecting the BMC with one or more networks.

3. The BMC of claim 2, further comprising a management module communicating first management transactions over the one or more networks wherein one or more of the networks is a management network exclusively used for second management transactions.

4. The BMC of claim 2, wherein the BMC receives power to operate hardware of the BMC through a network connection to the network module.

5. The BMC of claim 1, further comprising a second monitor module, the second monitor module receiving the operations parameters from the monitor module and providing a user with a notification of the operations parameters that are outside pre-established thresholds.

6. The BMC of claim 1, further comprising one or more boot device emulation modules, each boot device emulation module providing a bit stream to an associated computing element within the host computing device wherein each of the one or more boot device emulation modules represents itself as a boot device for the associated computing element and the bit streams provide for boot operation of the associated computing element.

7. The BMC of claim 6, wherein the bit stream is one of a plurality of stored bit streams having an associated compatibility profile, each boot device emulation module determining a configuration profile of the host computing device and providing to the associated computing element one bit stream having the associated compatibility profile consistent with the configuration profile of the host computing device.

8. The BMC of claim 1, further comprising a security module, the security module executing one or more of:

validating control messages and management messages sent to the BMC;

setting one or more host computing devices in a state compatible with system security requirements for one or more computing devices communicating with the host computing device; and

validating software and firmware code for the BMC and the one or more host computing devices.

9. The BMC of claim 1, further comprising an interrupt module configured to generate an interrupt message for transmission to one or more computing devices, and to receive an interrupt message from one or more computing devices, wherein the computing device is one of a local computing device and a remote computing device.

10. The BMC of claim 1, further comprising a logging module configured to store as data elements in non-volatile memory one or more of the operations parameters of the host computing device, recovery parameters, manufacturing parameters, security events, and environmental events, the logging module further assigning to each data element a storage classification defining permissions and storage characteristics.

11. The BMC of claim 2, further comprising an assignment module comprising:

a subtask module configured to divide a management task into a plurality of subtasks;

a delegation module configured to assign an execution order for the subtasks and to assign the subtasks to one or more BMCs communicatively connected to the BMC over the one or more networks;

a master module configured to receive response data from the one or more BMCs that received the subtasks from the delegation module; and

a subtask module configured to receive subtasks from a subtask-initiating BMC on the one or more networks, execute the received subtasks, and return response data to the subtask-initiating BMC.

12. The BMC of claim 1, further comprising an environmental control module configured to control power settings and temperature settings of the host computing device, wherein controlling comprises monitoring a temperature of the host computing device and adjusting one or more of the settings to put an environment of the host computing device in an environmental profile.

13. The BMC of claim 1, further comprising a system test module configured to execute one or more systems tests, the systems tests comprising one or more of a power on self test (POST), a diagnostics test, qualification test, and an acceptance test.

14. The BMC of claim 1, further comprising a scan ring module configured to transfer data between the BMC and one or more devices on the host computing device supporting scan ring access.

15. The BMC of claim 1, further comprising a code load module configured to request code from one of a local host computing device and an external device and store the code locally on the BMC.

16. The BMC of claim 15, wherein the BMC utilizes the code load module to boot itself from one of the local host computing device and the external device.

17. The BMC of claim 1, further comprising a programmable read only memory (PROM) having one or more boot images for the BMC, including one or more known good boot images, the BMC further comprising a boot module configured to load the known good boot image to the BMC after a failed load of the one or more boot images to the BMC.

18. The BMC of claim 17, further comprising an update module configured to store a current image in use on the BMC into the non-volatile memory in response to a command to load a new image to the BMC, the update module further configured to restore the current image from the non-volatile memory to the BMC in response to a failure in the new image.

19. The BMC of claim 2, further comprising a network boot module facilitating a network boot of the host computing device, the network boot module supplying network configuration information to the host computing device.

20. A system comprising:

one or more host computing devices comprising one or more computing elements connected to a system bus, each host computing device being configured to receive a baseboard management controller (BMC);

one or more BMCs comprising;

a reconfigurable field programmable gate array (FPGA) comprising a monitor module configured to monitor one or more operations parameters of the host computing device, the monitor module configured to be operationally independent of the host computing device;

a host connector configured to communicatively connect the BMC to the system bus of the host computing device, the system bus configured to provide connectivity between the one or more computing elements of the host computing device, the host connector further comprising a plurality of functionally reconfigurable pins, wherein a connection configuration of the functionally reconfigurable pins is established by the FPGA; and

a server module comprising a processor, non-volatile memory, and an operating system, the operating system configured to provide services of one or more modules to the host computing device, the server module configured to be operationally independent of the host computing device; and

a network module configured to communicatively connect the BMC with one or more networks;

wherein the host connector is configured to implement a plurality of different connection configurations based on logic programming of the FPGA, a particular connection configuration of the plurality corresponding to a communication protocol used by the system bus of the host computing device;

wherein the reconfigurable FPGA is configured to establish a first connection configuration of the plurality of different connection configurations and is configured to establish a second connection configuration of the plurality of connection configurations subsequent to establishing the first connection configuration and wherein when in the first connection configuration, a block of pins of the reconfigurable FPGA are configured to communicate over a PCI express connection and when in the second connection configuration, the block of pins of the reconfigurable FPGA are configured to communicate over an Ethernet connection;

wherein the BMC is configured to represent itself to the host computing device as a plurality of emulated computing devices, each of the emulated computing devices implemented by a different emulation module of the BMC, the emulation modules configured to share a connection to the system bus, and at least one of the emulation modules configured to represent itself as a network connection, to provide information about the network connection to the system bus, and to provide access to one or more of the emulated computing devices using the network connection such that an actual path and an emulated path of a request from the host computing device to the one or more of the emulated computing devices using the network connection are indistinguishable to the host computing device; and

one or more networks communicatively connecting the one or more BMCs.

21. The system of claim 20, further comprising one or more boot device emulation modules, each boot device emulation module providing a bit stream to an associated computing element within the host computing device.

22. The system of claim 21, wherein the bit stream is one of a plurality of stored bit streams having an associated compatibility profile, each boot device emulation module determining a configuration profile of the host computing device and providing to the associated computing element one bit stream having the associated compatibility profile consistent with the configuration profile of the host computing device.

23. A baseboard management controller module (BMC) comprising:

a reconfigurable field programmable gate array (FPGA) comprising a monitor module configured to monitor one or more operations parameters of a host computing device, the monitor module configured to be operationally independent of the host computing device;

a host connector configured to communicatively connect the BMC to a system bus of the host computing device, the system bus configured to provide connectivity between one or more computing elements of the host computing device, the host connector further comprising a plurality of functionally reconfigurable pins, wherein a connection configuration of the functionally reconfigurable pins is established by the FPGA;

a server module comprising a processor, non-volatile memory, and an operating system, the operating system configured to provide services of one or more modules to the host computing device, the server module configured to be operationally independent of the host computing device;

wherein the reconfigurable FPGA is configured to establish a plurality of connection configurations of the functionally reconfigurable pins of the host connector, a different one of the connection configurations being established for each of a plurality of different communications protocols, one of the communications protocols being used by the system bus of the host computing device;

wherein the reconfigurable FPGA is configured to establish a first connection configuration of the plurality of different connection configurations and is configured to establish a second connection configuration of the plurality of connection configurations subsequent to establishing the first connection configuration and wherein when in the first connection configuration, a block of pins of the reconfigurable FPGA are configured to communicate over a PCI express connection and when in the second connection configuration, the block of pins of the reconfigurable FPGA are configured to communicate over an Ethernet connection;

wherein the BMC is configured to represent itself to the host computing device as a plurality of emulated computing devices, each of the emulated computing devices implemented by a different emulation module of the BMC, the emulation modules configured to share a connection to the system bus, and at least one of the emulation modules configured to represent itself as a network connection, to provide information about the network connection to the system bus, and to provide access to one or more of the emulated computing devices using the network connection such that an actual path and an emulated path of a request from the host computing device to the one or more of the emulated computing devices using the network connection are indistinguishable to the host computing device; and

further comprising one or more boot device emulation modules, each boot device emulation module configured to provide a bit stream to an associated computing element within the host computing device wherein each of the one or more boot device emulation modules is configured to represent itself as a boot device for the associated computing element and the bit streams provide for boot operation of the associated computing element.