Set sampling controls instruction

• US 8,417,837 B2
• Filed: 10/11/2010
• Issued: 04/09/2013
• Est. Priority Date: 10/02/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bartik, Jane H., Heller, Lisa C., Osisek, Damian L., Schmidt, Donald W., West, Patrick M. Jr., Yeh, Phil C.
• Primary Examiner(s): RHU, KRIS M
• Application Number:
  US12/901,805
• Publication Number:
  US 20110029758A1
• Time in Patent Office: 911 Days
• Field of Search: None
• US Class Current: 710/5
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/461 Sector or disk block
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields

Abstract

A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

Claims

1. A computer program product for executing a machine instruction in a central processing unit, the computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

obtaining a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

an opcode field identifying a set sampling controls instruction; and

a first field identifying a general register, the contents of which are added to the contents of a second field to form a second operand address; and

executing the machine instruction, the executing comprising;

activating sampling for one or more sampling intervals to obtain information relating to processing of the central processing unit, wherein the activating sampling comprises at least one of activating basic sampling to obtain a set of architected sample data or activating diagnostic sampling to obtain a set of non-architected sample data; and

placing in one or more control registers one or more sampling controls of a request block located in one or more storage locations designated by the second operand address.

2. The computer program product of claim 1, wherein the set of architected sample data comprises at least one of an instruction address, a primary address space number and state information relating to the central processing unit.

3. The computer program product of claim 1, wherein the set of non-architected sample data comprises data relating to hardware design.

4. The computer program product of claim 1, wherein the activating sampling comprises activating basic sampling, and wherein the one or more control registers comprises information regarding one or more instructions executed by the central processing unit.

5. The computer program product of claim 1, wherein the request block comprises at least one of:

a size indicator field specifying a maximum buffer size indicator;

a host indicator, responsive to being set, specifying a host;

a basic sampling enable control, responsive to being set, specifying basic sampling;

a diagnostic sampling enable control, responsive to being set, specifying diagnostic sampling;

a basic sampling activation control, responsive to being set, specifying basic sampling activation;

a diagnostic sampling activation control, responsive to being set, specifying diagnostic sampling activation;

a sampling interval;

contents of a table entry address register; and

contents of a data entry address register.

6. The computer program product of claim 5, wherein one or more controls of the basic sampling enable control, the diagnostic sampling enable control, the basic sampling activation control or the diagnostic sampling activation control are set responsive to a basic sampling function and a diagnostic sampling function making a valid state transition.

7. The computer program product of claim 5, wherein the placing comprises placing the maximum buffer size indicator, the host indicator, the sampling interval, the contents of the table entry address register and the contents of the data entry address register in the one or more control registers, responsive to a sampling function being set to an active state.

8. The computer program product of claim 7, wherein the placing comprises placing the maximum buffer size indicator, the host indicator, the sampling interval, the contents of the table entry address register and the contents of the data entry address register in the one or more control registers, responsive to a sampling function being set to an active state and responsive to the sampling interval being within a supported range.

9. The computer program product of claim 5, wherein the executing comprises setting a condition code, wherein the condition code is set to 0 responsive to setting the basic sampling enable control, the diagnostic sampling enable control, the basic sampling activation control and the diagnostic sampling activation control.

10. The computer program product of claim 1, wherein the request block is 64 bytes and includes:

bit 0 specifying a maximum buffer size indicator;

bit 1 indicating a host, responsive to the central processing unit running at a logical partition level;

bit 54 specifying a basic sampling enable control;

bit 55 specifying a diagnostic sampling enable control;

bit 62 specifying a basic sampling activation control; and

bit 63 specifying a diagnostic sampling activation control.

11. The computer program product of claim 10, wherein the request block further includes:

a sampling interval;

contents of a table entry address register; and

contents of a data entry address register.

12. The computer program product of claim 1, wherein the request block comprises contents of a table entry address register, the contents of the table entry address register indicating a current entry of a sample data block, the current entry of the sample data block comprising at least one of a basic sampling data entry or a diagnostic sampling data entry.

13. The computer program product of claim 12, wherein the request block comprises contents of a data entry address register, the contents of the data entry address register indicating a next entry of the sample data block.

14. The computer program product of claim 12, wherein the basic sampling data entry comprises at least one of a number of unique instructions completed during a sampling cycle, and an address of an instruction executed during the sampling cycle.

15. The computer program product of claim 14, wherein the basic sampling data entry comprises at least one of a data entry format code, a data address translation mode, a wait state indicator, a problem state indicator, an address space control, an invalid indicator, and a primary address space number.

16. The computer program product of claim 15, wherein the basic sampling data entry comprises at least one of a host program parameter and a guest program parameter.

17. The computer program product of claim 12, wherein the diagnostic sampling data entry comprises non-architected sample data.

18. The computer program product of claim 17, wherein the diagnostic sampling data entry comprises at least one of a data entry format code, a maximum buffer size and an invalid indicator.

19. A computer system for executing a machine instruction in a central processing unit, the computer system comprising:

a memory; and

a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising;

obtaining a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

an opcode field identifying a set sampling controls instruction; and

a first field identifying a general register, the contents of which are added to the contents of a second field to form a second operand address; and

executing the machine instruction, the executing comprising;

activating sampling for one or more sampling intervals to obtain information relating to processing of the central processing unit, wherein the activating sampling comprises at least one of activating basic sampling to obtain a set of architected sample data or activating diagnostic sampling to obtain a set of non-architected sample data; and

placing in one or more control registers one or more sampling controls of a request block located in one or more storage locations designated by the second operand address.

20. The computer system of claim 19, wherein the set of architected sample data comprises at least one of an instruction address, a primary address space number and state information relating to the central processing unit.

21. The computer system of claim 19, wherein the set of non-architected sample data comprises data relating to hardware design.

22. The computer system of claim 19, wherein the request block comprises contents of a table entry address register, the contents of the table entry address register indicating a current entry of a sample data block, the current entry of the sample data block comprising at least one of a basic sampling data entry or a diagnostic sampling data entry.

23. The computer system of claim 22, wherein the request block comprises contents of a data entry address register, the contents of the data entry address register indicating a next entry of the sample data block.

24. A method of executing a machine instruction in a central processing unit, the method comprising:

obtaining a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

an opcode field identifying a set sampling controls instruction; and

a first field identifying a general register, the contents of which are added to the contents of a second field to form a second operand address; and

executing the machine instruction, the executing comprising;

activating sampling for one or more sampling intervals to obtain information relating to processing of the central processing unit, wherein the activating sampling comprises at least one of activating basic sampling to obtain a set of architected sample data or activating diagnostic sampling to obtain a set of non-architected sample data; and

placing in one or more control registers one or more sampling controls of a request block located in one or more storage locations designated by the second operand address.

25. The method of claim 24, wherein the request block comprises contents of a table entry address register, the contents of the table entry address register indicating a current entry of a sample data block, the current entry of the sample data block comprising at least one of a basic sampling data entry or a diagnostic sampling data entry.