Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector

• US 8,417,921 B2
• Filed: 08/31/2010
• Issued: 04/09/2013
• Est. Priority Date: 08/15/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Gonion, Jeffry E., Diefendorff, Keith E.
• Primary Examiner(s): VICARY, KEITH E
• Application Number:
  US12/873,043
• Publication Number:
  US 20100325398A1
• Time in Patent Office: 952 Days
• Field of Search: None
• US Class Current: 712/222
• CPC Class Codes: G06F 8/4441 Reducing the execution time required by the program code
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution

Abstract

The described embodiments provide a processor for generating a result vector that contains results from a comparison operation. During operation, the processor receives a first input vector, a second input vector, and a control vector. When subsequently generating a result vector, the processor first captures a base value from a key element position in the first input vector. For selected elements in the result vector, processor compares the base value and values from relevant elements to the left of a corresponding element in the second input vector, and writes the result into the element in the result vector. In the described embodiments, the key element position and the relevant elements can be defined by the control vector and an optional predicate vector.

Claims

1. A method for generating a result vector with results of a multi-way comparison operation, comprising:

in a processor, performing operations for;

receiving a first input vector, a second input vector, and a control vector, and optionally receiving a predicate vector, wherein each vector includes a same number of elements;

capturing a base value contained in an element of the first input vector at a key element position; and

generating the result vector, wherein generating the result vector involves, if the predicate vector is received, for each element in the result vector to the right of the key element position for which a corresponding element in the predicate vector is active, otherwise, for each element in the result vector to the right of the key element position,

setting the element in the result vector equal to a result of a multi-way comparison operation for which the inputs are the base value and a value in each relevant element of the second input vector from an element at the key element position to and including a predetermined element in the second input vector, wherein a relevant element in the second input vector is an element in the second input vector for which a corresponding element in the control vector is active.

2. The method of claim 1, wherein the multi-way comparison operation is one of:

a MIN operation for which a result of the multi-way comparison operation is a lowest of the compared values;

or

a MAX operation for which the result of the multi-way comparison operation is a highest of the compared values.

3. The method of claim 2, wherein the predetermined element in the second input vector is one of:

a closest element to the left of an element in a same position as the element in the result vector;

or

the element in the same position as the element in the result vector.

4. The method of claim 3, wherein generating the result vector involves setting an element in the result vector at the key element position equal to one of:

the base value;

or

a result of the multi-way comparison operation for which the inputs are the base value and a value in the key element position of the second input vector.

5. The method of claim 4, wherein if the predicate vector is received, the key element position is a leftmost element position where both the control vector and the predicate vector are active;

otherwise, the key element position is a leftmost element position where the control vector is active.

6. The method of claim 5, wherein the method further comprises:

if the predicate vector is received, for each element in the result vector to the left of the key element position for which a corresponding element in the predicate vector is active, otherwise, for each element in the result vector to the left of the key element position in the result vector, generating the result vector involves setting the element in the result vector equal to a value in a corresponding element in the first input vector; and

wherein if no key element position exists, if the predicate vector is received, for each element in the result vector for which a corresponding element in the predicate vector is active, otherwise, for each element in the result vector, generating the result vector involves setting the element in the result vector equal to a value in a corresponding element in the first input vector.

7. The method of claim 6, wherein if the predicate vector is received, generating the result vector involves, for each element in the result vector, if a corresponding element in the predicate vector is not active, one of:

leaving the element in the result vector unmodified;

or

setting the element in the result vector to zero.

8. The method of claim 1, wherein generating the result vector involves processing elements in the first input vector, the second input vector, the control vector, and, if the predicate vector is received, the predicate vector in parallel to enable the elements of the result vector to be generated in parallel.

9. A processor for generating a result vector with results from a multi-way comparison operation, comprising:

at least one execution unit configured to;

receive a first input vector, a second input vector, and a control vector, and optionally receive a predicate vector, wherein each vector includes a same number of elements;

capture a base value contained in an element of the first input vector at a key element position; and

generate the result vector, wherein when generating the result vector, if the predicate vector is received, for each element in the result vector to the right of the key element position for which a corresponding element in the predicate vector is active, otherwise, for each element in the result vector to the right of the key element position, the at least one execution unit is configured to;

set the element in the result vector equal to a result of the multi-way comparison operation for which the inputs are the base value and a value in each relevant element of the second input vector from an element at the key element position to and including a predetermined element in the second input vector, wherein a relevant element in the second input vector is an element in the second input vector for which a corresponding element in the control vector is active.

10. The processor of claim 9, wherein the multi-way comparison operation is one of:

a MIN operation for which a result of the multi-way comparison operation is a lowest of the compared values;

or

a MAX operation for which the result of the multi-way comparison operation is a highest of the compared values.

11. The processor of claim 10, wherein the predetermined element in the second input vector is one of:

a closest element to the left of an element at a same position as the element in the result vector;

or

the element at the same position as the element in the result vector.

12. The processor of claim 11, wherein when generating the result vector, the at least one execution unit is configured to set an element in the result vector at the key element position equal to one of:

the base value;

or

a result of the multi-way comparison operation for which the inputs are the base value and a value in the key element position of the second input vector.

13. The processor of claim 12, wherein if the predicate vector is received, the key element position is a leftmost element position where both the control vector and the predicate vector are active;

otherwise, the key element position is a leftmost element position where the control vector is active.

14. The processor of claim 13, wherein if the predicate vector is received, for each element in the result vector to the left of the key element position for which a corresponding element in the predicate vector is active, otherwise, for each element in the result vector to the left of the key element position in the result vector, when generating the result vector, the at least one execution unit is configured to set the element in the result vector equal to a value in a corresponding element in the first input vector;

and

wherein if no key element position exists, if the predicate vector is received, for each element in the result vector for which a corresponding element in the predicate vector is active, otherwise, for each element in the result vector, when generating the result vector the at least one execution unit is configured to set the element in the result vector equal to a value in a corresponding element in the first input vector.

15. The processor of claim 14, wherein if the predicate vector is received, when generating the result vector, for each element in the result vector, if a corresponding element in the predicate vector is not active, the at least one execution unit is configured to one of:

leave the element in the result vector unmodified;

or

set the element in the result vector to zero.

16. The processor of claim 9, wherein when generating the result vector, the at least one execution unit is configured to process elements in the first input vector, the second input vector, the control vector, and, if the predicate vector is received, the predicate vector in parallel to enable the elements of the result vector to be generated in parallel.

17. A computer system for generating a result vector with results from a multi-way comparison operation, comprising:

a processor;

a memory coupled to the processor, wherein the memory stores data and instructions for the processor;

at least one execution unit in the processor, wherein the at least one execution unit is configured to;

receive a first input vector, a second input vector, and a control vector, and optionally receive a predicate vector, wherein each vector includes a same number of elements;

capture a base value contained in an element of the first input vector at a key element position; and

generate the result vector, wherein when generating the result vector, if the predicate vector is received, for each element in the result vector to the right of the key element position for which a corresponding element in the predicate vector is active, otherwise, for each element in the result vector to the right of the key element position, the at least one execution unit is configured to;

set the element in the result vector equal to a result of the multi-way comparison operation for which the inputs are the base value and a value in each relevant element of the second input vector from an element at the key element position to and including a predetermined element in the second input vector, wherein a relevant element in the second input vector is an element in the second input vector for which a corresponding element in the control vector is active.

18. The computer system of claim 17, wherein the multi-way comparison operation is one of:

a MIN operation for which a result of the multi-way comparison operation is a lowest of the compared values;

or

a MAX operation for which the result of the multi-way comparison operation is a highest of the compared values.

19. The computer system of claim 18, wherein the predetermined element in the second input vector is one of:

a closest element to the left of an element in a same element position as the element in the result vector;

or

the element in the same element position as the element in the result vector.

20. The computer system of claim 19, wherein when generating the result vector, the at least one execution unit is configured to set an element in the result vector at the key element position equal to one of:

the base value;

or

a result of the multi-way comparison operation for which the inputs are the base value and a value in the key element position of the second input vector.

21. The computer system of claim 20, wherein if the predicate vector is received, the key element position is a leftmost element position where both the control vector and the predicate vector are active;

otherwise, the key element position is a leftmost element position where the control vector is active.

22. The computer system of claim 21, wherein if the predicate vector is received, for each element in the result vector to the left of the key element position for which a corresponding element in the predicate vector is active, otherwise, for each element in the result vector to the left of the key element position in the result vector, when generating the result vector, the at least one execution unit is configured to set the element in the result vector equal to a value in a corresponding element in the first input vector;

and

wherein if no key element position exists, if the predicate vector is received, for each element in the result vector for which a corresponding element in the predicate vector is active, otherwise, for each element in the result vector, when generating the result vector the at least one execution unit is configured to set the element in the result vector equal to a value in a corresponding element in the first input vector.

23. The computer system of claim 22, wherein if the predicate vector is received, when generating the result vector, for each element in the result vector, if a corresponding element in the predicate vector is not active, the at least one execution unit is configured to one of:

leave the element in the result vector unmodified;

or

set the element in the result vector to zero.

24. The computer system of claim 17, wherein when generating the result vector, the at least one execution unit is configured to process elements in the first input vector, the second input vector, the control vector, and, if the predicate vector is received, the predicate vector in parallel to enable the elements of the result vector to be generated in parallel.