Data signal handling circuitry and methods with error analysis capabilities

• US 8,418,046 B2
• Filed: 08/25/2008
• Issued: 04/09/2013
• Est. Priority Date: 02/13/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Yao, Wei, Gettemy, Shawn Robert, Corlett, Barry
• Primary Examiner(s): Bhatia, Ajay
• Assistant Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US12/229,685
• Publication Number:
  US 20090204860A1
• Time in Patent Office: 1,688 Days
• Field of Search: 714/707, 714/708, 714/724, 714/726
• US Class Current: 714/817
• CPC Class Codes: G09G 5/00 Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators image data processing or generation, in general G06T
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits

Abstract

Data receiver circuitry in the device is provided with one or more error signal output leads. An error signal on such a lead includes an error indication as soon as possible after the associated low level circuitry detects a data error. The timing of such an error indication is compared to the timing of noise from various possible noise sources in the device. The noise source that produced significant noise closest in time prior to the error indication is identified as the noise source responsible for the data error that caused the error indication.

Claims

1. An electronic device comprising:

a component configured to receive a data signal and process data from the signal through a series of circuit layers, beginning with a first circuit layer configured to initially receive the data signal, and ending with a second circuit layer configured to perform an application on data from the data signal, one of the series of circuit layers outputting from the component an error signal containing an error indication, the error signal being generated substantially concurrent with detection, by the one of the series of circuit layers, of a data error occurring in the data signal;

a lead configured to convey a noise signal containing noise indications substantially concurrent with noise produced by a noise source of the electronic device; and

processor circuitry configured to receive the error signal and the noise signal, and configured to compare timing of the error indication in the error signal and the noise indications in the noise signal, wherein the processor circuitry is configured to produce an output signal identifying the noise source as a possible cause of the error indication if the error indication has a predetermined timing relationship to the noise indication, and wherein the predetermined timing relationship requires the noise indication to be no more than a predetermined amount of time prior to the error indication.

2. The electronic device defined in claim 1 further comprising:

a first device output terminal to which the error signal is applied; and

a second device output terminal to which the lead is connected.

3. Apparatus comprising the electronic device defined in claim 2 and the circuitry external to the electronic device for receiving the error signal from the first device output terminal and the noise signal from the second device output terminal.

4. The apparatus defined in claim 3 wherein the circuitry external to the electronic device is adapted to compare timing of an error indication in the error signal and a noise indication in the noise signal.

5. The apparatus defined in claim 3 wherein the circuitry external to the electronic device is adapted to compare timing of an error indication in the error signal and a noise indication in the noise signal.

6. The electronic device defined in claim 1 further comprising:

a plurality of leads, each conveying a respective one of a plurality of noise signals, each of the noise signals containing noise indication substantially concurrent with noise produced by a respective one of a plurality of noise sources.

7. The electronic device defined in claim 6 further comprising:

processor circuitry for receiving the error signal and the noise signals, and for comparing timing of an error indication in the error signal and the noise indications in the noise signals.

8. The electronic device defined in claim 7 wherein the processor circuitry produces an output signal identifying, as a possible cause of the error indication, a one of the noise sources for which the noise signal contained a noise indication having a predetermined timing relationship to the error indication.

9. The electronic device defined in claim 8 wherein the predetermined relationship requires the noise indication to be no more than a predetermined amount of time prior to the error indication.

10. The electronic device defined in claim 6 further comprising:

a first device output terminal to which the error signal is applied; and

a plurality of second device output terminals to which the leads are respectively connected.

11. Apparatus comprising the electronic device defined in claim 10 and circuitry external to the electronic device for receiving the error signal from the first device output terminal and the plurality of noise signals from the plurality of second device output terminals.

12. The apparatus defined in claim 11 wherein the circuitry external to the electronic device is adapted to display the error signal and the plurality of noise signals plotted against a common time base.

13. The apparatus defined in claim 11 wherein the apparatus external to the electronic device is adapted to compare timing of an error indication in the error signal and the noise indications in the plurality of noise signals.

14. The electronic device defined in claim 1 wherein the first circuit layer comprises physical layer circuitry.

15. The electronic device defined in claim 14 wherein the circuit layers comprises an intermediate level circuit layer that is intermediate to the first circuit layer and the second circuit layer, and wherein the intermediate level circuit layer outputs from the component a second error signal containing an error indication substantially concurrent with the intermediate level circuit layer detecting a data error in the data signal.

16. The electronic device defined in claim 15 further comprising:

a lead configured to convey a noise signal containing noise indications substantially concurrent with noise produced by a noise source of the electronic device; and

processor circuitry configured to receive the error signal, the second error signal, and the noise signal, and configured to compare timing of the error indication in either of the error signal or the second error signal and the noise indication in the noise signal.

17. The electronic device defined in claim 1 wherein the component comprises a display of the electronic device.

18. A method of testing an electronic device including a component configured to receive a data signal and process data from that data signal through a series of circuit layers, beginning with a first circuit layer configured to initially receive the data signal, and ending with a second circuit layer configured to perform an application on the data from the data signal, the method comprising:

causing one of the series of circuit layers to output from the component an error signal containing an error indication, the error signal being generated substantially concurrent with detection, by the one of the series of circuit layers, of a data error occurring in the data signal; and

comparing timing of the error indication in the error signal and a noise indication in a noise signal, the noise signal containing noise indications substantially concurrent with noise produced by a noise source of the electronic device, wherein comparing the timing of the error indication in the error signal and the noise indication in the noise signal comprises determining whether the noise indication is within a predetermined time interval prior to the error indication.

19. The method defined in claim 18 wherein the comparing comprises:

further comparing timing of the error indication in the error signal and the noise indications in each of a plurality of noise signals, each of the plurality of noise signals containing noise indications substantially concurrent with noise produced by a respective one of a plurality of noise sources of the electronic device.

20. The method defined in claim 19 wherein the further comparing comprises:

determining whether the noise indication in any of the noise signals is within a predetermined time interval prior to the error indication, and if so, identifying the noise source for that noise signal as a possible cause of the error indication.

21. The method defined in claim 18 wherein the causing comprises outputting the error signal from physical layer circuitry of the component.