Method of manufacture for a semiconductor device

• US 8,420,483 B2
• Filed: 01/08/2008
• Issued: 04/16/2013
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Primary Examiner(s): Tran, Tony
• Application Number:
  US11/971,169
• Publication Number:
  US 20080166845A1
• Time in Patent Office: 1,925 Days
• Field of Search: 438/147, 257/E21.41, 257/329, 257/E29.257
• US Class Current: 438/270
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/2003 characterised by the substrate
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66537 : using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer.

Claims

1. A process for making a transistor, comprising the actions, in any order except as specified below, of:

in a semiconductor material, forming a source region having a first conductivity type, a body region having a second conductivity type, and a drift region having said second conductivity type, wherein said drift region has a lower doping density than said body region;

forming at least one trench extending downward into said drift region of said semiconductor material;

forming a dielectric layer on the inner surface of the trench; and

thereafter

introducing ions in said dielectric layer to produce a substantially stable density of ions in proximity to sidewalls of said trench, to thereby produce an intentionally introduced fixed net electrostatic charge; and

thereafter

substantially filling said trench with dielectric material, forming a recess in said trench, and forming a gate electrode in said recess which is capacitively coupled to said body region;

wherein said introducing step provides a density of said ions, in proximity to said drift region in said semiconductor material, which inverts the surface of said drift region of said semiconductor material;

wherein said introducing step also introduces ions into the bottom of said trench;

wherein said ions are cesium ions; and

wherein said semiconductor material is an epitaxial structure built on a substrate, and said trench extends into said epitaxial structure but not into said substrate.

2. The process of claim 1, wherein said introducing step is performed by ion implantation.

3. The process of claim 1, wherein said semiconductor material is silicon.

4. The process of claim 1, wherein said gate electrode is a doped polycrystalline semiconductor material.

5. A process for making a transistor, comprising the actions, in any order except as specified below, of:

in a semiconductor material, forming a source region having a first conductivity type, a body region having a second conductivity type, and a drift region having said second conductivity type, wherein said drift region has a lower doping density than said body region;

forming at least one trench extending downward into said drift region of said semiconductor material;

forming a dielectric layer on the inner surface of the trench; and

thereafter

introducing ions in said dielectric layer to produce a stable density of net electrostatic charge in proximity to sidewalls of said trench, in sufficient concentration to invert at least part of said semiconductor material adjacent to said trench; and

thereafter

filling said trench with dielectric material, forming a recess in said trench, and forming a gate electrode in said recess which is capacitively coupled to said body region;

wherein said introducing step also introduces ions into the bottom of said trench;

wherein said ions are cesium ions; and

wherein said semiconductor material is an epitaxial structure built on a substrate, and said trench extends into said epitaxial structure but not into said substrate.

6. The process of claim 5, wherein said introducing step is performed by ion implantation.

7. The process of claim 5, wherein said filling step fills said trench completely.

8. The process of claim 5, wherein said filling step fills said trench completely without any voids.

9. The process of claim 5, wherein said filling step fills said trench without any voids.