Group III-V semiconductor device and method for producing the same

• US 8,420,502 B2
• Filed: 02/22/2010
• Issued: 04/16/2013
• Est. Priority Date: 03/16/2007
• Status: Expired due to Fees

• Current Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Original Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Inventors: Ando, Masanobu, Horiuchi, Shigemi, Kinoshita, Yoshinori, Tomita, Kazuyoshi
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US12/656,970
• Publication Number:
  US 20100151612A1
• Time in Patent Office: 1,149 Days
• Field of Search: 257/88, 257/E33.023, 257/E33.06, 438/22, 438/24, 438/26, 438/28, 438/29, 438/978
• US Class Current: 438/458
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.

Claims

1. A method for producing a Group III-V semiconductor device, the method comprising:

forming, on a base, a plurality of semiconductor devices isolated from one another;

forming, through an ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device;

after the forming of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on a top surface of the semiconductor device;

bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer comprising at least one selected from a group consisting of Au—

Sn, Au—

Si, Ag—

Sn—

Cu, and Sn—

Bi; and

removing the base through a laser lift-off process,

wherein the side surface of the semiconductor device is formed to be inclined so that the device has a cross-sectional area gradually increasing toward the base, and the ion implantation is performed along a direction normal to a main plane of the base.

2. The method of claim 1, further comprising:

after said removing the base, performing the ion implantation into a portion of the semiconductor device from a surface which has previously bonded to the base, the portion being in a vicinity of the side surface.

3. The method of claim 1, further comprising;

after said removing the base, forming a dielectric material insulating film on a portion of a surface of the semiconductor device which has previously bonded to the base, the portion being in a vicinity of the side surface.

4. A method for producing a Group III-V semiconductor device, the method comprising:

forming, on a base, a plurality of semiconductor devices isolated from one another;

forming, through an ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device;

after the forming of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on a top surface of the semiconductor device;

bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and

removing the base through a laser lift-off process,

wherein the side surface of the semiconductor device is formed to be inclined so that the device has a cross-sectional area gradually increasing toward the base, and ion implantation is performed along a direction normal to the main plane of the base,

wherein the ion implantation is performed at an acceleration voltage which allows implanted ions to reach the base so that a width of the high-resistance region increases toward the base, the width being in a direction parallel to the base.

5. The method of claim 4, wherein the low-melting-point metal layer comprises at least one selected from a group consisting of Au—

Sn, Au—

Si, Ag—

Sn—

Cu, and Sn—

Bi.

6. The method of claim 4, wherein the width of the high-resistance region continuously increases as the high-resistance region extends from an upper surface of the high-resistance region to the base.

7. The method of claim 4, wherein a cross-sectional shape of the high-resistance region, extending perpendicular to the base, comprises a right-angled triangle.

8. A method for producing a Group III-V semiconductor device, the method comprising:

forming, on a base, a plurality of semiconductor devices isolated from one another;

forming, through an ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device;

after the faulting of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on a top surface of the semiconductor device;

bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer;

removing the base through a laser lift-off process; and

after said removing the base, fowling an n-electrode on a surface of the semiconductor device which has previously bonded to the base, and performing the ion implantation into the surface of the semiconductor device through the n-electrode, which serves as a mask.

9. A method for producing a Group III-V semiconductor device, the method comprising:

forming a Group III-V semiconductor layer on a base;

forming a high-resistance region in a predetermined portion of the semiconductor layer through an ion implantation from a top surface thereof at an acceleration voltage which allows implanted ions to reach the base to isolate the semiconductor layer, through the high-resistance region, into semiconductor device regions isolated from one another;

after the forming of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of at least the semiconductor device regions;

bonding the semiconductor device regions to a conductive support substrate via a low-melting-point metal layer; and

removing the base through a laser lift-off process.

10. A semiconductor device production method as described in claim 9, wherein the semiconductor device comprises a Group III nitride semiconductor device.

11. A semiconductor device production method as described in claim 9, wherein the semiconductor device comprises a light-emitting device.

12. A semiconductor device production method as described in claim 9, wherein after said removing the base, a portion of the high-resistance region between adjacent semiconductor device regions is etched and the conductive support substrate is cut in an etched portion to obtain individual semiconductor devices.

13. A semiconductor device production method as described in claim 9, wherein the p-electrode and the low-melting-point metal diffusion prevention layer are formed on an entirety of the top surface of the semiconductor layer.

14. A semiconductor device production method as described in claim 9, wherein the low-melting-point metal layer comprises at least one selected from a group consisting of Au—

Sn, Au—

Si, Ag—

Sn—

Cu, and Sn—

Bi.

15. A method for producing a Group III-V semiconductor device, the method comprising:

forming, on a base, a plurality of semiconductor devices isolated from one another;

forming, through an ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device;

after the forming of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on a top surface of the semiconductor device;

bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and

removing the base through a laser lift-off process,

wherein the side surface of the semiconductor device is formed to be inclined so that the device has a cross-sectional area gradually increasing toward the base, and ion implantation is performed along a direction normal to the main plane of the base, and

wherein the ion implantation is performed at an acceleration voltage which allows implanted ions to reach the base and the ion implantation is performed at a plurality of times at different acceleration voltages.

16. A method for producing a Group III-V semiconductor device, the method comprising:

forming a Group III-V semiconductor layer on a base;

forming a first high-resistance region in a predetermined portion of the semiconductor layer through an ion implantation from a top surface thereof at an acceleration voltage which does not allow implanted ions to reach the base;

after the forming of the first high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor layer;

bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer;

removing the base through a laser lift-off process; and

forming, in addition to the first high-resistance region, a second high-resistance region in the predetermined portion of the semiconductor layer from a surface which has previously bonded to the base, the portion corresponding to the first high-resistance region, through an ion implantation at an acceleration voltage which allows implanted ions to reach the first high-resistance region to isolate the semiconductor layer, through the first and second high-resistance regions, into semiconductor device regions isolated from one another.

17. A semiconductor device production method as described in claim 16, wherein after said removing the base, a portion of the first and second high-resistance regions between adjacent semiconductor device regions is etched and the conductive support substrate is cut in an etched portion to obtain individual semiconductor devices.

18. A semiconductor device production method as described in claim 16, wherein the p-electrode and the low-melting-point metal diffusion prevention layer are formed on an entirety of the top surface of the semiconductor layer.

19. A semiconductor device production method as described in claim 16, wherein the low-melting-point metal layer comprises at least one selected from a group consisting of Au—

Sn, Au—

Si, Ag—

Sn—

Cu, and Sn—

Bi.