Semiconductor device and manufacturing method thereof

• US 8,421,068 B2
• Filed: 10/14/2010
• Issued: 04/16/2013
• Est. Priority Date: 10/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Miyake, Hiroyuki, Takahashi, Kei, Toyotaka, Kouhei, Tsubuku, Masashi, Noda, Kosei, Kuwabara, Hideaki
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Newton, Valerie N
• Application Number:
  US12/904,565
• Publication Number:
  US 20110089414A1
• Time in Patent Office: 915 Days
• Field of Search: None
• US Class Current: 257/43
• CPC Class Codes: G06K 19/07758 arrangements for adhering the record carrier to further objects or living beings, functioning as an identification tag
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 21/8236 Combination of enhancement and depletion transistors
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/26 including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

Claims

1. A semiconductor device comprising:

a substrate having an insulating surface;

a first gate electrode layer over the substrate;

a first electrode layer over the substrate;

a first gate insulating layer over the first gate electrode layer and the first electrode layer;

an oxide semiconductor layer over the first gate insulating layer;

a first insulating layer over the first electrode layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

a second gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

a second gate electrode layer over the second gate insulating layer,

wherein at least part of the drain electrode layer overlaps with the first electrode layer, and

wherein the first insulating layer and the first gate insulating layer are provided between the drain electrode layer and the first electrode layer.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a CPU.

3. The semiconductor device according to claim 1, wherein the semiconductor device is an LSI.

4. The semiconductor device according to claim 1, wherein the semiconductor device is a DRAM.

5. The semiconductor device according to claim 1,

wherein a hydrogen concentration in the oxide semiconductor layer is lower than or equal to 5×

10¹⁹ atoms/cm³, and

wherein a carrier concentration in the oxide semiconductor layer is lower than or equal to 5×

10¹⁴/cm³.

6. The semiconductor device according to claim 1, wherein the semiconductor device is an EDMOS circuit.

7. A semiconductor device comprising an EDMOS circuit comprising:

a substrate having an insulating surface;

a first thin film transistor over the substrate; and

a second thin film transistor over the substrate,

wherein the first thin film transistor comprises;

a first gate electrode layer;

a first gate insulating layer over the first gate electrode layer;

an first oxide semiconductor layer over the first gate insulating layer;

a first source electrode layer and a first drain electrode layer over the first oxide semiconductor layer;

a second gate insulating layer over the first oxide semiconductor layer, the first source electrode layer, and the first drain electrode layer; and

a second gate electrode layer over the second gate insulating layer,

wherein the second thin film transistor comprises;

a first insulating layer;

a second oxide semiconductor layer over the first insulating layer;

a second source electrode layer and a second drain electrode layer over the second oxide semiconductor layer;

a third gate insulating layer over the second oxide semiconductor layer, the second source electrode layer, and the second drain electrode layer; and

a third gate electrode layer over the third gate insulating layer,

wherein the first drain electrode layer is electrically connected to the second source electrode layer, and

wherein the third gate electrode layer is electrically connected to the second source electrode layer.

8. The semiconductor device according to claim 7, wherein an off-current value in each of the first thin film transistor and the second thin film transistor is less than or equal to 1×

10<sup>−

13</sup> A.

9. The semiconductor device according to claim 7,

wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×

10¹⁹ atoms/cm³, and

wherein a carrier concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×

10¹⁴/cm³.

10. The semiconductor device according to claim 7,

wherein a channel length of the first thin film transistor is longer than a channel length of the second thin film transistor.

11. The semiconductor device according to claim 7,

wherein a thickness of the first oxide semiconductor layer is smaller than a thickness of the second oxide semiconductor layer.

12. The semiconductor device according to claim 7, wherein the semiconductor device is a CPU.

13. The semiconductor device according to claim 7, wherein the semiconductor device is an LSI.

14. The semiconductor device according to claim 7, wherein the semiconductor device is a DRAM.