Memory device

• US 8,421,071 B2
• Filed: 01/09/2012
• Issued: 04/16/2013
• Est. Priority Date: 01/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Hatano, Takehisa
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US13/345,834
• Publication Number:
  US 20120181534A1
• Time in Patent Office: 463 Days
• Field of Search: 257/43, 257/E29.296, 257/E29.309, 257/314, 257/315
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A memory device in which a write error can be prevented is provided. The memory device includes a NAND cell unit including a plurality of memory cells connected in series, a first selection transistor connected to one of terminals of the NAND cell unit, a second selection transistor connected to the other of the terminals of the NAND cell unit, a source line connected to the first selection transistor, and a bit line which intersects with the source line and is connected to the second selection transistor. In the memory device, a channel region of each of the first selection transistor and the second selection transistor is formed in an oxide semiconductor layer.

Claims

1. A memory device comprising:

a NAND cell unit including a plurality of memory cells connected in series;

a first selection transistor connected to a first terminal of the NAND cell unit;

a second selection transistor connected to a second terminal of the NAND cell unit;

a source line connected to the first selection transistor; and

a bit line connected to the second selection transistor,

wherein each of the first selection transistor and the second selection transistor comprises an oxide semiconductor layer including a channel region,

wherein the first selection transistor overlaps with the NAND cell unit with an insulating layer interposed between the first selection transistor and the NAND cell unit, and

wherein the second selection transistor overlaps with the NAND cell unit with the insulating layer interposed between the second selection transistor and the NAND cell unit.

2. The memory device according to claim 1, wherein the oxide semiconductor layer comprises two or more elements selected from In, Ga, Sn, and Zn.

3. The memory device according to claim 1,

wherein each of the plurality of memory cells comprises a transistor, and

wherein a channel region of the transistor comprises a silicon.

4. The memory device according to claim 1,

wherein each of the plurality of memory cells comprises a transistor, and

wherein the transistor comprises a channel region formed in a semiconductor substrate.

5. A memory device comprising:

a NAND cell unit including a plurality of memory cells connected in series;

a first selection transistor provided between a first terminal of the NAND cell unit and a source line; and

a second selection transistor provided between a second terminal of the NAND cell unit and a bit line,

wherein the first selection transistor is connected to the first terminal of the NAND cell unit and the source line,

wherein the second selection transistor is connected to the second terminal of the NAND cell unit and the bit line,

wherein each of the first selection transistor and the second selection transistor comprises an oxide semiconductor layer including a channel region,

wherein the first selection transistor overlaps with the NAND cell unit with an insulating layer interposed between the first selection transistor and the NAND cell unit, and

wherein the second selection transistor overlaps with the NAND cell unit with the insulating layer interposed between the second selection transistor and the NAND cell unit.

6. The memory device according to claim 5, wherein the oxide semiconductor layer comprises two or more elements selected from In, Ga, Sn, and Zn.

7. The memory device according to claim 5,

wherein each of the plurality of memory cells comprises a transistor, and

wherein a channel region of the transistor comprises a silicon.

8. The memory device according to claim 5,

wherein each of the plurality of memory cells comprises a transistor, and

wherein the transistor comprises a channel region formed in a semiconductor substrate.

9. A memory device comprising:

a NAND cell unit including a plurality of memory cells connected in series;

a first selection transistor; and

a second selection transistor,

wherein a first terminal of the first selection transistor is connected to a source line,

wherein a second terminal of the first selection transistor is connected to a first terminal of the NAND cell unit,

wherein a first terminal of the second selection transistor is connected to a bit line,

wherein a second terminal of the second selection transistor is connected to a second terminal of the NAND cell unit, and

wherein each of the first selection transistor and the second selection transistor comprises an oxide semiconductor layer including a channel region,

wherein the first selection transistor overlaps with the NAND cell unit with an insulating layer interposed between the first selection transistor and the NAND cell unit, and

wherein the second selection transistor overlaps with the NAND cell unit with the insulating layer interposed between the second selection transistor and the NAND cell unit.

10. The memory device according to claim 9, wherein the oxide semiconductor layer comprises two or more elements selected from In, Ga, Sn, and Zn.

11. The memory device according to claim 9,

wherein each of the plurality of memory cells comprises a transistor, and

wherein a channel region of the transistor comprises a silicon.

12. The memory device according to claim 9,

wherein each of the plurality of memory cells comprises a transistor, and

wherein the transistor comprises a channel region formed in a semiconductor substrate.

13. A memory device comprising:

a first transistor;

a second transistor;

a third transistor comprising a first floating gate electrode;

a fourth transistor comprising a second floating gate electrode;

a source line electrically connected to one of a source and a drain of the first transistor; and

a bit line electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor through the third transistor and the fourth transistor,

wherein the third transistor and the fourth transistor are connected in series between the first transistor and the second transistor,

wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer including a channel region, and

wherein the third transistor and the fourth transistor does not comprise an oxide semiconductor layer.

14. The memory device according to claim 13, wherein the oxide semiconductor layer comprises two or more elements selected from In, Ga, Sn, and Zn.

15. The memory device according to claim 13,

wherein each of channel regions of the third transistor and the fourth transistor comprises a silicon.

16. The memory device according to claim 13, wherein the first transistor and the second transistor are provided over the third transistor and the fourth transistor.

17. The memory device according to claim 13, wherein a region of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor is shared with each other.

18. A memory device comprising:

a first transistor;

a second transistor;

a third transistor comprising a first floating gate electrode;

a fourth transistor comprising a second floating gate electrode;

a source line electrically connected to one of a source and a drain of the first transistor; and

a bit line electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor through the third transistor and the fourth transistor,

wherein the third transistor and the fourth transistor are connected in series between the first transistor and the second transistor,

wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer including a channel region, and

wherein each of the third transistor and the fourth transistor comprises a channel region formed in a semiconductor substrate.

19. The memory device according to claim 18, wherein the oxide semiconductor layer comprises two or more elements selected from In, Ga, Sn, and Zn.

20. The memory device according to claim 18,

wherein each of the channel regions of the third transistor and the fourth transistor comprises a silicon.

21. The memory device according to claim 18, wherein the first transistor and the second transistor are provided over the third transistor and the fourth transistor.

22. The memory device according to claim 18, wherein a region of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor is shared with each other.