Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC)

• US 8,421,073 B2
• Filed: 01/14/2011
• Issued: 04/16/2013
• Est. Priority Date: 10/26/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Hung-Chih, Wang, Mill-Jer, Peng, Ching-Nen, Chen, Hao
• Primary Examiner(s): Pham, Long
• Application Number:
  US13/006,639
• Publication Number:
  US 20120097944A1
• Time in Patent Office: 823 Days
• Field of Search: 257/48, 257/686, 257/758, 257/E23.002
• US Class Current: 257/48
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/0237 Disposition of the redistribution layers
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16155 the item being non-metallic, e.g. being an insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded.

Claims

1. A test structure for chained through silicon vias (TSVs) on a substrate, said test structure comprising:

a plurality of TSVs extending from a first surface of the substrate to a second surface opposite to the first surface, wherein the plurality of TSVs are chained together by interconnect, and

a plurality of test pads, wherein at least one of the plurality of test pads is grounded to the substrate, and wherein the remaining of the plurality of test pads are either connected to the chained TSVs or are grounded.

2. The test structure of claim 1, wherein the interconnect that chains the plurality of TSVs includes structures in a redistribution layer.

3. The test structure of claim 1, wherein the plurality of test pads includes five test pads, with one test pad grounded to the substrate, two test pads connected to one end of the chained TSVs and the remaining two test pads connected to the other end of the chained TSVs.

4. The test structure of claim 1, wherein the test structure is configured to perform electrical tests to determine the quality and properties of the plurality of TSVs on the substrate.

5. The test structure of claim 1, wherein the test structure is configured to test frequency, resistance, capacitance and leakage of the chained TSVs.

6. The test structure of claim 1, wherein the number of the plurality of TSVs is equal to or greater than about 2.

7. The test structure of claim 1, wherein the plurality of TSVs are chained together in a daisy chain.

8. The test structure of claim 3, comprising more than one test areas, and wherein each of the test areas has the five test pads.

9. The test structures of claim 8, wherein the plurality of TSVs of the substrate are chained together in each of the test areas, and the TSVs chained in one of the test areas are further chained to the TSVs chained in another test area, for enabling testing of the chained TSVs both in each test area and across multiple said test areas.

10. The test structure of claim 1, wherein the test structure is inside a die of the substrate.

11. The test structure of claim 1, further comprising:

a frequency multiplier; and

a frequency divider, wherein the frequency multiplier and the frequency divider are connectable to the chained TSVs for allowing high frequency tests to be performed on the TSVs by the test structure.

12. The test structure of claim 1, wherein the interconnect includes at least one of a redistribution structure of a redistribution layer, a metal layer, or a via.

13. The test structured of claim 1, wherein the test structure include a plurality of test regions, and wherein the TSVs in one of the plurality of test regions have a first size and a first pitch, and the TSVs in another one of the plurality of the test regions have a second size and a second pitch, and wherein at least one of the second size or the second pitch is different from the first size or first pitch, respectively.

14. A test structure to test a three dimensional integrated circuit (3DIC), the test structure comprising:

a first substrate with a plurality of first through silicon vias (TSVs) and at least five test pads, wherein the plurality of first TSVs are chained together through interconnect, wherein one of the five test pads is grounded to the substrate, and wherein two of the remaining four test pads are electrically connected to one of the plurality of first TSVs and the remaining two test pads are electrically connected to another one of the plurality of first TSVs; and

a second substrate, wherein the second substrate are bonded to the first substrate through metal bumps.

15. The test structure of claim 14, wherein the metal bumps are aligned with the plurality of first TSVs.

16. The test structure of claim 14, wherein at least a portion of interconnect that chains the plurality of first TSVs is on the second substrate.

17. The test structure of claim 14, wherein the test structure is configured to test frequency, resistance, capacitance and leakage of the plurality of first TSVs.

18. The test structure of claim 14, wherein the second substrate includes a plurality of second TSVs, wherein the plurality of second TSVs align with the plurality of first TSVs, respectively, and wherein the plurality of second TSVs and the plurality of first TSVs are chained together for electrical testing.

19. The test structure of claim 14, further comprising a third substrate, wherein the third substrate is sandwiched between the first substrate and the second substrate, wherein the third substrate has a plurality of third TSVs, wherein the plurality of third TSVs align with the plurality of first TSVs, respectively, and wherein the first, second, and third substrates are bonded together by metal bumps.

20. The test structure of claim 14, wherein the grounded test pad is grounded to the substrate through interconnect for grounding which spreads across an area with the plurality of first TSVs.