Memory device, memory module and electronic device
First Claim
1. A memory device comprising:
- a memory cell comprising a first transistor, a second transistor, and a first insulating film,wherein the first transistor comprises;
a first oxide semiconductor layer including a first channel formation region;
a first electrode connected to the first oxide semiconductor layer;
a second electrode connected to the first oxide semiconductor layer;
a first gate electrode overlapping with the first channel formation region; and
a second insulating layer interposed between the first gate electrode and the first oxide semiconductor layer,wherein the second transistor comprises;
a second gate electrode;
a third insulating film over the second gate electrode;
a second oxide semiconductor layer including a second channel formation region over the third insulating film;
a third electrode connected to the second oxide semiconductor layer;
a fourth electrode connected to the second oxide semiconductor layer;
a fourth insulating film over the second oxide semiconductor layer, the third electrode, and the fourth electrode; and
a third gate electrode over the fourth insulating film,wherein the second gate electrode, the third gate electrode, and the second channel formation region are overlapped with each other,wherein the first oxide semiconductor layer is located above the third gate electrode, andwherein the first oxide semiconductor layer is located above the first insulating film, and the second oxide semiconductor layer is located below the first insulating film.
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Accused Products
Abstract
The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.
156 Citations
18 Claims
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1. A memory device comprising:
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a memory cell comprising a first transistor, a second transistor, and a first insulating film, wherein the first transistor comprises; a first oxide semiconductor layer including a first channel formation region; a first electrode connected to the first oxide semiconductor layer; a second electrode connected to the first oxide semiconductor layer; a first gate electrode overlapping with the first channel formation region; and a second insulating layer interposed between the first gate electrode and the first oxide semiconductor layer, wherein the second transistor comprises; a second gate electrode; a third insulating film over the second gate electrode; a second oxide semiconductor layer including a second channel formation region over the third insulating film; a third electrode connected to the second oxide semiconductor layer; a fourth electrode connected to the second oxide semiconductor layer; a fourth insulating film over the second oxide semiconductor layer, the third electrode, and the fourth electrode; and a third gate electrode over the fourth insulating film, wherein the second gate electrode, the third gate electrode, and the second channel formation region are overlapped with each other, wherein the first oxide semiconductor layer is located above the third gate electrode, and wherein the first oxide semiconductor layer is located above the first insulating film, and the second oxide semiconductor layer is located below the first insulating film. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory device comprising:
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a memory cell comprising a first transistor, a second transistor, and a first insulating film, wherein the first transistor comprises; a first oxide semiconductor layer including a first channel formation region; a first electrode connected to the first oxide semiconductor layer; a second electrode connected to the first oxide semiconductor layer; a first gate electrode overlapping with the first channel formation region; and a second insulating layer interposed between the first gate electrode and the first oxide semiconductor layer, wherein the second transistor comprises; a second gate electrode; a third insulating film over the second gate electrode; a second oxide semiconductor layer including a second channel formation region over the third insulating film; a third electrode connected to the second oxide semiconductor layer; a fourth electrode connected to the second oxide semiconductor layer; a fourth insulating film over the second oxide semiconductor layer, the third electrode, and the fourth electrode; and a third gate electrode over the fourth insulating film, wherein the second gate electrode, the third gate electrode, and the second channel formation region are overlapped with each other, wherein the first oxide semiconductor layer is located above the third gate electrode, wherein the first oxide semiconductor layer is located above the first insulating film, and the second oxide semiconductor layer is located below the first insulating film, and wherein an area where the first oxide semiconductor layer overlaps with the first gate electrode is smaller than that where the second oxide semiconductor layer overlaps with the second gate electrode or the third gate electrode. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification