Integrated CMOS and MEMS with air dielectric method and system

• US 8,421,082 B1
• Filed: 01/18/2011
• Issued: 04/16/2013
• Est. Priority Date: 01/19/2010
• Status: Active Grant

• Current Assignee: Movella Incorporated (Movella Holdings, Inc.)
• Original Assignee: mCube, Inc.
• Inventors: Yang, Xiao Charles
• Primary Examiner(s): Weiss, Howard
• Assistant Examiner(s): Rao, Steven
• Application Number:
  US13/008,870
• Time in Patent Office: 819 Days
• Field of Search: 257/69, 257/288, 257/E21.421
• US Class Current: 257/69
• CPC Class Codes: B81B 2207/094 Feed-through, via
• CPC Class Codes: B81B 7/0038 using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A method and structure for fabricating a monolithic integrated CMOS and MEMS device. The method includes providing a first semiconductor substrate having a first surface region and forming one or more CMOS IC devices on a CMOS IC device region overlying the first surface region. The CMOS IC device region can also have a CMOS surface region. A bonding material can be formed overlying the CMOS surface region to form an interface by which a second semiconductor substrate can be joined to the CMOS surface region. The second semiconductor substrate having a second surface region to the CMOS surface region by bonding the second surface region to the bonding material, the second semiconductor substrate comprising one or more first air dielectric regions. One or more free standing MEMS structures can be formed within one or more portions of the processed first substrate.

Claims

1. A method for fabricated a monolithic integrated CMOS and MEMS device, the method comprising:

providing a first semiconductor substrate having a first surface region;

forming one or more CMOS integrated circuit devices provided on a CMOS integrated circuit device region overlying the first surface region, the CMOS integrated circuit device region having a CMOS surface region;

forming a dielectric layer overlying the CMOS surface region;

joining a second semiconductor substrate having a second surface region to the CMOS surface region by bonding the second surface region to the dielectric layer, the second semiconductor being patterned such that one or more portions of the second semiconductor substrate within a vicinity of the one or more CMOS integrated devices are removed to form one or more first air dielectric regions;

thinning the first substrate to a desired thickness while maintaining attachment to the CMOS integrated device region; and

forming one or more free standing MEMS structures overlying one or more portions of the desired thickness of the first semiconductor substrate.

2. The method of claim 1 wherein the first semiconductor substrate is selected from a group consisting of:

a buried oxide (BOX), layer overlying a silicon substrate, an epitaxial (EPI) layer overlying a silicon substrate, an amorphous silicon substrate, a single crystal silicon substrate, and a polycrystalline silicon substrate.

3. The method of claim 1 wherein the dielectric layer is a top oxide layer.

4. The method of claim 1 wherein the dielectric layer is formed via a chemical mechanical planarization (CMP) process.

5. The method of claim 1 wherein the thinning comprises:

using a grinding process to remove a thickness of material from the first semiconductor substrate to expose a ground surface region;

subjecting the ground surface region to a polishing process to smooth the ground surface region to a predetermined surface roughness; and

monitoring a thickness of the first substrate during either or both the grinding process and/or the polishing process.

6. The method of claim 5 wherein the monitoring comprises using an interferometer process to measure an indication associated with the thickness of the first semiconductor substrate, the interferometer process using an electromagnetic radiation in an infrared wavelength range.

7. The method of claim 1 wherein the thinning process comprises a grinding process to remove a thickness of material from the first semiconductor substrate to expose a ground surface region;

and further comprising applying a blanket etching process to the first semiconductor substrate.

8. The method of claim 1 wherein the thinning comprises a grinding process to remove a thickness of material from the first semiconductor substrate to expose a ground surface region;

and further comprising a patterned etching process such that one or more portions of the first semiconductor substrate within a vicinity of the one or more CMOS integrated circuit devices are removed to form one or more second air dielectric regions.

9. The method of claim 1 further comprising forming one or more via structures within one or more portions of the first semiconductor substrate, the one or more via structures extending from one or more portions of the CMOS integrated circuit device region to a vicinity of the desired thickness of the first semiconductor substrate, the one or more via structures being configured as one or more stop structures to form one or more end point regions of the thinning.

10. The method of claim 1 wherein the first semiconductor substrate is an SOI substrate comprising a bulk portion, overlying insulating layer, and a single crystal device layer;

and wherein the thinning comprises selectively removing the bulk portion of the SOI substrate from the single crystal device layer while maintaining attachment to the CMOS integrated circuit device region.

11. The method of claim 1 wherein the thinning comprises cleaving a portion of the first semiconductor substrate at a cleave region to remove the desired thickness from the first semiconductor substrate, the cleave region being within a vicinity of the desired thickness, the desired thickness being a remaining portion of the first semiconductor substrate attached to the CMOS integrated circuit device region.

12. The method of claim 1 wherein the CMOS integrated circuit device region is formed using a standing CMOS process from a semiconductor foundry.

13. The method of claim 1 further comprising forming a sacrificial layer overlying the one or more free standing MEMS structures.

14. The method of claim 13 further comprising forming an enclosure layer overlying the sacrificial layer, the enclosure layer having one or more openings to expose one or more portions of the sacrificial layer.

15. The method of claim 14 wherein the enclosure layer comprises a titanium material, the titanium material being activated as a getter layer.

16. The method of claim 14 wherein the enclosure layer is selected from a group consisting of:

a metal material, a semiconductor material, an amorphous silicon material, and a dielectric material.

17. The method of claim 14 further comprising removing the sacrificial layer via an ashing process to form an open region between the one or more free standing MEMS structures and the enclosure layer;

and forming an encapsulating layer overlying the enclosure layer to substantially seal the one or more free standing MEMS structures to form a predetermined environment within the open region.

18. The method of claim 17 wherein the encapsulating layer is selected from a group consisting of:

a metal layer, a spin on glass, a spray on glass, amorphous silicon, and a dielectric layer.

19. The method of claim 17 wherein the encapsulating layer is formed overlying the sacrificial layer overlying the one or more free standing MEMS structures.

20. The method of claim 17 wherein the predetermined environment comprises an inert gas at a determined pressure.

21. The method of claim 14 further comprising forming one or more bond pad openings to expose one or more bond pads coupled to the CMOS device layer.

22. The method of claim 1 further comprising forming an enclosure housing the one or more free standing MEMS structures, the enclosure configured overlying a first outer region of the desired thickness of the first semiconductor substrate, the enclosure having an upper cover region.

23. The method of claim 22 further comprising forming one or more bonding structures, each of the bonding structures having a bonding pad within a vicinity of the upper cover region and provided within a second outer region of the thickness of the first semiconductor substrate.

24. The method of claim 1 wherein the one or more MEMS devices are selected from a group consisting of:

an accelerometer, a gyroscope, a magnetic sensor, a pressure sensor, a microphone, a humidity sensor, a temperature sensor, a chemical sensor, a biosensor, and an inertial sensor.

25. The method claim 1 wherein the one or more bonding structures comprises the bonding pad, a via structure, and a pad structure, the pad structure being integrally coupled to the one or more CMOS integrated circuit devices.

26. The method of claim 1 wherein each of the bonding structures is spatially disposed such that a spacing is provided between each of the bonding structures and the enclosure.

27. The method of claim 1 wherein the one or more free standing MEMS structures are spatially disposed such that there is an opening provided between the enclosure and the one or more free standing MEMS structures.

28. The method of claim 27 wherein the opening is filled with one or more gases.