Apparatus and method for diffusion sensing

• US 8,421,438 B2
• Filed: 07/27/2010
• Issued: 04/16/2013
• Est. Priority Date: 06/07/2010
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Pratt, Ryan M, Couglar, Karl J, Homol, David K
• Primary Examiner(s): NGUYEN, HOAI AN D
• Application Number:
  US12/844,301
• Publication Number:
  US 20110298444A1
• Time in Patent Office: 994 Days
• Field of Search: 324/76.11, 324/713, 324/522, 702/1, 702/57, 702/64, 702/116, 702/117, 702/127
• US Class Current: 324/76.11
• CPC Class Codes: G05F 1/468 characterised by reference voltage circuitry, e.g. soft start, remote shutdown
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/34 Negative-feedback-circuit arrangements with or without positive feedback H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence ; for rejection of common mode signals H03F3/45479
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/21131 the input bias voltage of a power amplifier being controlled, e.g. by a potentiometer or an emitter follower
• CPC Class Codes: H03F 2203/21139 An impedance adaptation circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 2203/7215 the gated amplifier being switched on or off by a switch at the input of the amplifier
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 3/30 : in amplifiers having semiconductor devices
• CPC Class Codes: H03G 3/3042 : in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H03H 11/30 : Automatic matching of source impedance to load impedance
• CPC Class Codes: H03K 17/6872 : using complementary field-effect transistors
• CPC Class Codes: H04B 1/40 : Circuits

Abstract

Apparatuses and methods for diffusion sensing are disclosed. In one embodiment, an apparatus includes a complimentary metal oxide semiconductor (CMOS) switch and a switch sense block. The switch includes a gate, a drain, a source, and a well. The source and drain are formed in the well. The gate is formed adjacent the well between the source and drain, and the source is configured to receive a bias voltage from a power amplifier. The switch sense block is configured to measure a signal indicative of the voltage of at least one of the source or drain voltage of the switch and to generate an output signal based on the measurement.

Claims

1. An apparatus for sensing a bias voltage of a switch, the apparatus comprising:

a complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well, the source and drain formed in the well, the gate formed adjacent the well between the source and drain, and the source configured to receive a bias voltage from a power amplifier;

a switch sense block configured to measure a signal indicative of the voltage of at least one of the source or drain of the switch and to generate an output signal based on the measurement; and

a well bias control block for biasing the well of the switch, the well bias control block configured to bias the well to at least two voltage levels.

2. The apparatus of claim 1 wherein the well has a p-type doping and the switch includes an n-well for electrically isolating the well from a substrate.

3. The apparatus of claim 1 wherein the switch sense block is configured to measure a signal indicative of the source voltage of the switch.

4. The apparatus of claim 1 wherein the switch sense block is configured to measure a signal indicative of the drain voltage of the switch.

5. The apparatus of claim 1 wherein the switch sense block comprises a filter for filtering the measured signal to produce a filtered signal and a voltage detector for generating the output signal based at least partly upon the voltage level of the filtered signal.

6. The apparatus of claim 5 wherein the filter is a low pass filter.

7. The apparatus of claim 6 wherein the filter is a RC filter.

8. The apparatus of claim 6 wherein the voltage detector is an inverter.

9. The apparatus of claim 1 wherein the switch and the power amplifier are disposed on separate dies.

10. The apparatus of claim 1 wherein the well bias control block is configured to select the voltage level for biasing the well based at least partly on the output signal of the switch sense block.

11. The apparatus of claim 1 wherein the well bias control block comprises at least one charge pump.

12. The apparatus of claim 1 further comprising a resistor having a first end electrically connected to the source of the switch and a second end electrically connected to the drain of the switch.

13. A method for sensing a bias voltage of a CMOS switch configured to receive a radio frequency signal from a power amplifier, the method comprising:

measuring a signal indicative of at least one of a source voltage or a drain voltage of the switch;

generating an output signal based on the measurement; and

biasing a well of the switch using a well bias control block, the well bias control block configured to bias the well to at least two voltage levels.

14. The method of claim 13 further comprising biasing the well of the switch to a voltage level corresponding to a disabled state of the well.

15. The method of claim 13 wherein measuring the signal comprises measuring the source voltage of the switch.

16. The method of claim 13 wherein measuring the signal comprises measuring the drain voltage of the switch.

17. The method of claim 13 further comprising filtering the measured signal to generate a filtered signal.

18. The method of claim 14 further comprising biasing the well of the switch to a voltage level corresponding to an enabled state of the well based at least partly on the output signal.

19. The method of claim 18 wherein biasing the well to an enabled state comprises biasing the voltage level of the well using a charge pump.

20. The method of claim 19 further comprising providing the charge pump a first power supply and providing the power amplifier a second power supply, wherein the first power supply and second power supply are different power supplies.

21. The method of claim 17 wherein generating the output signal comprises comparing the filtered signal to a reference signal.

22. The method of claim 21 wherein generating the output signal comprises comparing the filtered signal to a trip point of an inverter.

23. An apparatus for sensing a bias voltage, the apparatus comprising:

a complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well, the source and drain formed in the well, the gate formed adjacent the well between the source and drain, and the source configured to receive a bias voltage from a power amplifier;

means for measuring a signal indicative of the voltage of at least one of the source or drain of the switch;

means for generating an output signal based on the measurement; and

means for biasing the well of the switch, the well biasing means configured to bias the well to at least two voltage levels.

24. A computer-readable storage medium comprising instructions that when executed by a processor perform a method for sensing a bias voltage of a CMOS switch having a gate, a drain, a source, and a well, the source and drain formed in the well, the gate formed adjacent the well between the source and drain, and the source configured to receive a bias voltage from a power amplifier, the method comprising:

instructing a well bias control block to bias the well of the switch, the well bias control block configured to bias the well to at least two voltage levels;

receiving a signal indicative of the voltage of at least one of the source or drain of the switch; and

generating an output signal based on the received signal.