Charge pump circuit with low clock feed-through

• US 8,421,509 B1
• Filed: 10/25/2011
• Issued: 04/16/2013
• Est. Priority Date: 10/25/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Chien-Liang, Mou, Ya-Nan, Chen, Yuan-Hui, Chang, Yu-Jen
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US13/280,366
• Publication Number:
  US 20130099852A1
• Time in Patent Office: 539 Days
• Field of Search: 327/148, 327/156, 327/157, 327/536, 375/374
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop

Abstract

A charge pump circuit includes a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror, a first PMOS transistor and a first NMOS switch. The first PMOS switch is coupled between the PMOS tuner and a first output PMOS transistor of the first current mirror, thus the parasitic capacitor formed between the gate and the drain of the first PMOS switch, the parasitic capacitor formed between the gate and the source of the first output PMOS transistor, and the parasitic capacitor formed between the gate and the drain of the first output PMOS transistor are equivalently coupled in series, lowering the capacitance between the PMOS tuner and the charge pump output, and reducing the clock feed through and the charge injection effect in the charge pump circuit.

Claims

1. A charge pump circuit comprising:

a first comparator having a first input end, a second input end, and an output end coupled to the second input end of the first comparator;

a PMOS tuner having a source coupled to a voltage source, and a gate for receiving a first bias voltage;

a first current mirror comprising;

a source PMOS transistor having a source coupled to the voltage source, and a gate coupled to a drain of the source PMOS transistor; and

a first output PMOS transistor having a gate coupled to the gate of the source PMOS transistor, and a drain coupled to the first input of the first comparator;

a first NMOS transistor having a drain coupled to the gate of the first output PMOS transistor, a gate coupled to the output end of the first comparator, and a source coupled to ground;

a first PMOS switch having a drain coupled to the source of the first output PMOS transistor, a source coupled to a drain of the PMOS tuner, and a gate for receiving a first control signal;

an NMOS tuner having a source coupled to ground, and a gate for receiving a second bias voltage;

a second current mirror comprising;

a source NMOS transistor having a source coupled to ground, and a gate coupled to a drain of the source NMOS transistor; and

a first output NMOS transistor having a gate coupled to the gate of the source NMOS transistor, and a drain coupled to the first input of the first comparator;

a first PMOS transistor having a drain coupled to the gate of the first output NMOS transistor, a gate coupled to the output end of the first comparator, and a source coupled to the voltage source; and

a first NMOS switch having a drain coupled to the source of the first output NMOS transistor, a source coupled to the drain of the NMOS tuner, and a gate for receiving a second control signal.

2. The charge pump circuit of claim 1, wherein the first control signal is a logical inverse of the second control signal.

3. The charge pump circuit of claim 1 further comprising:

a second PMOS switch having a drain coupled to the source of the source PMOS transistor, a source coupled to the voltage source, and a gate coupled to the gate of the first NMOS transistor; and

a second NMOS switch having a drain coupled to the source of the source NMOS transistor, a source coupled to ground, and a gate coupled to the gate of the first PMOS transistor.

4. The charge pump circuit of claim 1 further comprising:

a second comparator having a first input end coupled to the first input end of the first comparator, a second input end, and an output end coupled to the second input end of the second comparator;

a third PMOS switch having a source coupled to the drain of the PMOS tuner, and a gate for receiving a third control signal; and

a third NMOS switch having a source coupled to the drain of the NMOS tuner, and a gate for receiving a fourth control signal;

wherein the first current mirror further comprises a second output PMOS transistor having a source coupled to a drain of the third PMOS switch, a drain coupled to the output end of the second comparator, and a gate coupled to the gate of the first output PMOS transistor; and

wherein the second current mirror further comprises a second output NMOS transistor having a source coupled to a drain of the third NMOS switch, a drain coupled to the drain of the second output PMOS transistor, and a gate coupled to the gate of the first output NMOS transistor.

5. The charge pump circuit of claim 4 further comprising:

a second PMOS switch having a drain coupled to the source of the source PMOS transistor, a source coupled to the voltage source, and a gate coupled to the gate of the first NMOS transistor; and

a second NMOS switch having a drain coupled to the source of the source NMOS transistor, a source coupled to ground, and a gate coupled to the gate of the first PMOS transistor.

6. The charge pump circuit of claim 4, wherein the first control signal is a logical inverse of the second control signal and the third control signal, and the second control signal is a logical inverse of the fourth control signal.