Decoding circuit and decoding method thereof

• US 8,421,652 B2
• Filed: 10/29/2010
• Issued: 04/16/2013
• Est. Priority Date: 11/26/2009
• Status: Expired due to Fees

• Current Assignee: MY-Semi Inc. (Diodes Incorporated)
• Original Assignee: MY-Semi Inc. (Diodes Incorporated)
• Inventors: Kuo, Chun-Ting, Lin, Chun-Fu, Hsieh, Cheng-Han
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US12/915,068
• Publication Number:
  US 20110121748A1
• Time in Patent Office: 900 Days
• Field of Search: 341 50-107, 375/354, 375/376, 315/291
• US Class Current: 341/53
• CPC Class Codes: H03M 7/006 using diodes

Abstract

A decoding circuit is adapted for decoding an input signal. The input signal includes at least a break and the time length of the break is a preset time. The decoding circuit includes a decoding unit and a detecting unit. The detecting unit detects whether the voltage level of the input signal is kept at a specific logic level for more than the preset time. If the input signal is kept at the specific logic level for more than the preset time, the detecting circuit, according to the voltage level of the specific logic level, outputs the input signal or the inverted input signal to the decoding unit so as to perform a decoding process.

Claims

1. A decoding circuit, adapted for decoding an input signal, wherein the input signal corresponds to a DMX512 signal format, the input signal comprises at least a break, and the length of the break is a preset time, the decoding circuit comprising:

a decoding unit; and

a detecting unit, coupled to the decoding unit, configured for detecting whether the input signal is kept at a specific logic level for more than the preset time;

wherein, when the input signal is kept at the specific logic level for more than the preset time, the detecting unit, according to the voltage level of the specific logic level, determines to output the input signal or the inverted input signal to the decoding unit to perform a decoding process.

2. The decoding circuit as claimed in claim 1, wherein,

when the specific logic level is at a logic high level, the detecting unit outputs the received input signal to the decoding unit;

and

when the specific logic level is at a logic low level, the detecting unit outputs the inverted input signal to the decoding unit.

3. The decoding circuit as claimed in claim 1, wherein the detecting unit comprising:

a multiplexer, having a first input terminal, a second input terminal and a selecting terminal, wherein the first input terminal received the input signal;

a inverter, coupled between the second input terminal and the input signal, configured for inverting the input signal and outputting the inverted input signal to the second input terminal; and

a level detecting unit, coupled to the selector terminal of the multiplexer and the input signal, configured for detecting whether the input signal is kept at the specific logic level for more than the preset time, and controlling the multiplexer according to the voltage level of the specific logic level so as to make the multiplexer to output the input signal or the inverted input signal.

4. The decoding circuit as claimed in claim 3, wherein,

when the specific logic level is at a logic high level, the multiplexer outputs the received input signal to the decoding unit;

and

when the specific logic level is at a logic low level, the multiplexer outputs the inverted input signal to the decoding unit.

5. The decoding circuit as claimed in claim 3, wherein the decoding unit is a DMX512 decoder.

6. The decoding circuit as claimed in claim 1, wherein the detecting unit detects whether a mark located before the break is over the preset time.

7. A decoding method, adapted for a decoding circuit to decode an input signal, wherein the input signal corresponds to a DMX512 signal format, the input signal comprises at least a break, and the length of the break is a preset time, the decoding method comprising:

receiving the input signal; and

detecting whether the input signal is kept at a specific logic level for more than the preset time;

wherein, when the input signal is kept at the specific logic level for more than the preset time, outputting the input signal or the inverted input signal to a decoding unit in the decoding circuit to perform a decoding process according to the voltage level of the specific logic level.

8. The decoding method as claimed in claim 7, wherein,

when the specific logic level is at a logic high level, the received input signal is output to the decoding unit;

and

when the specific logic level is at a logic low level, the inverted input signal is output to the decoding unit.

9. The decoding method as claimed in claim 7, wherein the decoding unit is a DMX512 decoder.

10. The decoding method as claimed in claim 7, wherein the step of detecting whether the input signal is kept at the specific logic level for more than the preset time further comprises:

detecting whether a mark located before the break is over the preset time.

11. The decoding method as claimed in claim 7, wherein the decoding circuit is integrated in a LED driver chip.