Minimum differential non-linearity trim DAC

• US 8,421,659 B2
• Filed: 02/24/2011
• Issued: 04/16/2013
• Est. Priority Date: 02/11/2011
• Status: Active Grant

• Current Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Inventors: von Staudt, Hans Martin
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US12/932,376
• Publication Number:
  US 20120206283A1
• Time in Patent Office: 782 Days
• Field of Search: 341/120, 341/121, 341/144
• US Class Current: 341/121
• CPC Class Codes: H03M 1/0692 using a diminished radix representation, e.g. radix 1.95
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/74 Simultaneous conversion

Abstract

A trim DAC wherein the digital input bits to the trim DAC are controlled by a state machine to produce an analog output that is within a least significant bit of the digital input bits. An undersize factor between digital input bits is used to assist in finding a trim solution for major transitions of the digital input bits. Trim solutions are stored in a nonvolatile memory associated with the state machine to be used in creating an accurate analog output.

Claims

1. A method of trimming an analog value using a trim DAC, comprising:

a) measuring an analog output of a trim DAC;

b) forming an nth bit, wherein an undersize factor of an analog equivalence between the nth bit and an n−

1 bit of the trim DAC narrows a distribution of a value of said analog output;

c) forming a difference factor between logically adjacent binary bits that is an undersized fraction of a normal difference; and

d) reducing a probability of a major transition between digital bits greater than a least significant bit.

2. A method of trimming an analog value using a trim DAC, comprising:

a) measuring an analog output of a trim DAC; and

b) forming an nth bit, wherein an undersize factor of an analog equivalence between the nth bit and an n−

1 bit of the trim DAC narrows a distribution of a value of said analog output and wherein said undersize factor is less than one and greater than zero.

3. A method of trimming an analog value using a trim DAC, comprising:

a) measuring an analog output of a trim DAC; and

b) forming an nth bit, wherein an undersize factor of an analog equivalence between the nth bit and an n−

1 bit of the trim DAC narrows a distribution of a value of said analog output and wherein said undersize factor between bits is applied to bits between a most significant bit and a second least significant bit of the digital input of said trim DAC.

4. A method of trimming an analog value using a trim DAC, comprising:

a) measuring an analog output of a trim DAC; and

b) forming an nth bit, wherein an undersize factor of an analog equivalence between the nth bit and an n−

1 bit of the trim DAC narrows a distribution of a value of said analog output and wherein said undersize factor between bits is applied to a first M most significant bits.

5. A method of trimming an analog value using a trim DAC, comprising:

a) measuring an analog output of a trim DAC; and

b) forming an nth bit, wherein an undersize factor of an analog equivalence between the nth bit and an n−

1 bit of the trim DAC narrows a distribution of a value of said analog output and wherein said undersize factor between bits is replaced with an oversize of a last L least significant bits.

6. A trim DAC, comprising:

a) a first binary trim bit;

b) a second binary trim bit, wherein said second binary trim bit forms a next more significant binary trim bit to said first binary trim bit;

c) said next more significant binary trim bit an undersized fraction of a normal difference factor between logically adjacent binary bits; and

d) said undersize fraction reduces the probability of a major transition greater than a least significant bit.

7. The trim DAC of claim 6, wherein said undersize fraction is a fraction (less than one and greater than zero) of the normal difference factor between logically adjacent binary bits.

8. The trim DAC of claim 6, wherein said undersize fraction is applied to all binary trim bits except a least significant binary trim bit.

9. The trim DAC of claim 6, wherein said undersize fraction is applied to most significant trim bits.

10. The trim DAC of claim 9, wherein the most significant trim bits are a most significant trim bit and a next most significant trim bit.

11. The trim DAC of claim 6, wherein said undersize fraction is applied in a unit value of the least significant bit and applied to more significant trim bits higher in significance than a second least significant trim bit.

12. The trim DAC of claim 6, wherein said first binary trim bit is a least significant bit and said second binary trim bit is a next least significant bit, wherein an oversize factor is applied to the first and second binary trim bits.

13. The trim DAC of claim 12, wherein the oversize factor maintains a range of the trim DAC at an expense of a wider trim distribution.