Analog-to-digital converter comprising dual oscillators for linearity compensation

• US 8,421,663 B1
• Filed: 02/15/2011
• Issued: 04/16/2013
• Est. Priority Date: 02/15/2011
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Bennett, George J.
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US13/027,557
• Time in Patent Office: 791 Days
• Field of Search: 341/143, 341/144, 341/118, 341/155, 341/157
• US Class Current: 341/155
• CPC Class Codes: H03M 1/0612 over the full range of the converter, e.g. for correcting differential non-linearity
• CPC Class Codes: H03M 1/0678 using additional components or elements, e.g. dummy components
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

An analog-to-digital converter (ADC) is disclosed operable to convert a sensor signal to a digital value. A differential amplifier responsive to the sensor signal and a reference signal generates a first analog signal representing a first offset above the reference signal and a second analog signal representing a second offset below the reference signal. A first oscillator generates a first output frequency dependent on the first analog signal, and a second oscillator generates a second output frequency dependent on the second analog signal. A difference between the first output frequency and the second output frequency is generated, and the digital value representing the sensor signal is generated in response to the difference.

Claims

1. An analog-to-digital converter (ADC) operable to convert a sensor signal to a digital value, the ADC comprising:

a differential amplifier responsive to the sensor signal and a reference signal, the differential amplifier operable to generate a first analog signal representing a first offset above the reference signal and a second analog signal representing a second offset below the reference signal;

a first oscillator comprising a first output frequency dependent on the first analog signal;

a second oscillator comprising a second output frequency dependent on the second analog signal; and

control circuitry operable to;

generate a difference between the first output frequency and the second output frequency; and

generate the digital value representing the sensor signal in response to the difference.

2. The ADC as recited in claim 1, wherein the first oscillator comprises a first ring oscillator and the second oscillator comprises a second ring oscillator.

3. The ADC as recited in claim 2, wherein the first ring oscillator is substantially matched to the second ring oscillator.

4. The ADC as recited in claim 1, wherein the difference between the first output frequency and the second output frequency compensates for a non-linearity of the first and second oscillators.

5. The ADC as recited in claim 1, wherein the control circuitry comprises:

a first counter driven by the first output frequency; and

a second counter driven by the second output frequency,

wherein the difference is generated in response to a difference between the first and second counters.

6. The ADC as recited in claim 1, wherein the control circuitry is further operable to adjust the reference signal in response to the first and second output frequencies.

7. The ADC as recited in claim 6, wherein the control circuitry is further operable to adjust the reference signal in response to a sum of the first and second output frequencies.

8. The ADC as recited in claim 7, wherein the control circuitry comprises:

a first counter driven by the first output frequency; and

a second counter driven by the second output frequency,

wherein the sum is generated in response to a sum of the first and second counters.

9. The ADC as recited in claim 8, wherein the control circuitry is further operable to adjust a sensor for generating the sensor signal in response to the sum.

10. A method of converting a sensor signal to a digital value, the method comprising:

generating a first analog signal representing a first offset above a reference signal and a second analog signal representing a second offset below the reference signal;

using a first oscillator to generate a first output frequency dependent on the first analog signal;

using a second oscillator to generate a second output frequency dependent on the second analog signal;

generating a difference between the first output frequency and the second output frequency; and

generating the digital value representing the sensor signal in response to the difference.

11. The method as recited in claim 10, wherein the first oscillator comprises a first ring oscillator and the second oscillator comprises a second ring oscillator.

12. The method as recited in claim 11, wherein the first ring oscillator is substantially matched to the second ring oscillator.

13. The method as recited in claim 10, wherein the difference between the first output frequency and the second output frequency compensates for a non-linearity of the first and second oscillators.

14. The method as recited in claim 10, further comprising:

driving a first counter with the first output frequency;

driving a second counter with the second output frequency; and

generating the difference in response to a difference between the first and second counters.

15. The method as recited in claim 10, further comprising adjusting the reference signal in response to the first and second output frequencies.

16. The method as recited in claim 15, further comprising adjusting the reference signal in response to a sum of the first and second output frequencies.

17. The method as recited in claim 16, further comprising:

driving a first counter with the first output frequency;

driving a second counter with the second output frequency; and

generating the sum in response to a sum of the first and second counters.

18. The method as recited in claim 17, further comprising adjusting a sensor for generating the sensor signal in response to the sum.