Liquid crystal display device

• US 8,421,791 B2
• Filed: 11/25/2009
• Issued: 04/16/2013
• Est. Priority Date: 11/25/2008
• Status: Active Grant

• Current Assignee: Japan Display Central Incorporated (Japan Display Incorporated), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Japan Display Central Incorporated (Japan Display Incorporated), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Harada, Kenji
• Primary Examiner(s): OLSON, JASON C
• Application Number:
  US12/625,808
• Publication Number:
  US 20100128019A1
• Time in Patent Office: 1,238 Days
• Field of Search: None
• US Class Current: 345/212
• CPC Class Codes: G06F 3/147 using display panels
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes

Abstract

A liquid crystal display device includes a plurality of pixels arranged on a substrate in a matrix, a source driver circuit to supply source signals to source lines connected to each pixel arranged in a column direction and a gate driver circuit to supply gate signals to respective gate lines connected to pixels arranged in a row direction. A control circuit outputs an array control signal for a partial display to a receiver circuit that receives a partial display start address to specify a gate line for starting a partial display and a partial display end address to specify a gate line for ending the partial display. A decoder circuit outputs a control signal to control a range of the gate lines driven by the gate driver circuit.

Claims

1. A liquid crystal display device, comprising:

a plurality of pixels arranged on a substrate in a matrix;

a source driver circuit to supply source signals to source lines connected to each pixel arranged in a column direction;

a gate driver circuit to supply gate signals to gate lines connected to each pixels arranged in a row direction;

a control circuit to output an array control signal for a partial display;

a receiver circuit to receive a serial data including a display mode signal, a partial display start address to specify a gate line for starting a partial display and a partial display end address to specify a gate line for ending the partial display and display data; and

a decoder circuit to output a control signal to control a range of gate lines driven by the gate driver circuit, and

wherein the receiver circuit comprises a serial-parallel converter circuit including shift registers to receive a serial data and a display mode memory, a start address memory, an end address memory and display data memory connected to the serial parallel converter circuit.

2. The liquid crystal display device according to claim 1, wherein the decoder circuit includes a partial start address decoder circuit and a partial end address decoder circuit to receive a partial display start address and a partial display end address and outputs control signals to control a gate driver circuit to select the specified gate lines for the partial display.

3. The liquid crystal display device according to claim 1, wherein the decoder circuit includes partial start and partial end address decoder circuits and a plurality of first and second lines arranged in a matrix wiring pattern and contact holes formed at crossing points to selectively connect the first and second lines, and

wherein the first lines are connected to the start and end address storing memories in the receiver circuit.

4. The liquid crystal display device according to claim 3, wherein the second lines are connected to a logic circuit to output complimentary control signals.

5. The liquid crystal display device according to claim 4, wherein the decoder circuit includes a switching circuit to select gate lines for a partial display on receiving the complementary control signals.

6. The liquid crystal display device according to claim 5, wherein the gate driver circuit includes shift registers.

7. The liquid crystal display device according to claim 6, wherein the gate driver circuit includes buffer circuits connected between the shift registers and gate lines, respectively.

8. The liquid crystal display device according to claim 4, wherein the logic circuit is an AND gate circuit.

9. A method for displaying a partial picture in a liquid crystal display panel, comprising the steps of:

outputting an array control signal for a partial display to a receiver circuit;

retrieving a start gate address and an end gate address from the receiver circuit;

decoding the start gate address and the end gate address to control a range to scan gate lines corresponding to a partial display area;

selecting gate lines for the partial display by controlling switches on receiving results of the decoding; and

supplying image data to the pixels selected by the gate lines to conduct a partial display, and

wherein the retrieving step comprises using a serial-parallel converter circuit formed of shift registers to receive a serial data including the start gate address and the end gate address, and storing respective portions of the array control signal in a display mode memory, a start address memory, an end address memory and display data memory.

10. A method for displaying first and second pictures in a liquid crystal display panel, the liquid crystal display panel including a pixel memory circuit in each of the pixels, comprising:

outputting an array control signal for a partial display to a receiver circuit;

retrieving a start gate address and an end gate address from the receiver circuit;

decoding the start gate address and the end gate address to control a range to scan gate lines corresponding to a partial display area;

selecting gate lines for the partial display by controlling switches on receiving results of the decoding;

supplying image data to the pixels selected by the gate lines to conduct a partial display; and

displaying the first and second pictures by different display standards having different number of gate lines.

11. The method according to claim 10, wherein the display standards are selected from NTSC, PAL and HD.

12. The method according to claim 10, wherein the start address and the end address are different depending on display standards having different number of scan lines.

13. A liquid crystal display device, comprising

a plurality of pixels arranged on a substrate in a matrix;

a source driver circuit to supply source signals to source lines connected to each pixel arranged in a column direction;

a gate driver circuit to supply gate signals to gate lines connected to each pixel arranged in a row direction;

a control circuit to output an array control signal for a partial display;

a receiver circuit to receive serial data including a display mode signal, a partial display start address to specify a gate line for starting a partial display, a partial display end address to specify a gate line for ending the partial display, and display data, the receiver circuit including a serial-parallel converter circuit formed of shift registers to receive serial data, a display mode memory, a start address memory, an end address memory, and a display data memory;

a decoder circuit to output a control signal to control a range of the gate lines driven by the gate driver circuit; and

a partial display control circuit to read the stored display mode signals to judge if the image data is a whole display or a partial display based on the display mode signal, and

wherein when the display is a partial display, the partial start and the partial end addresses stored in the start address memory and in the end address memory respectively are respectively outputted to the decoder circuit, and when the display is a whole display, an address of a first gate line is stored in the start address memory and an address of the last gate line is stored in the end address memory to scan all the gate lines, respectively.

14. The liquid crystal display device according to claim 13, wherein the partial display control circuit modifies the input start and end addresses so as to fit to the size of the display panel and stores the modified addresses in respective of the start address and end address memories.

15. The liquid crystal display device according to claim 13, wherein the array control signal is constructed by three control signals compliant to three lines serial interface protocol (SPI:

Serial Peripheral Interface).

16. The liquid crystal display device according to claim 13, wherein the pixels include a SRAM.