Self-powered event detection device

• US 8,422,293 B2
• Filed: 11/12/2010
• Issued: 04/16/2013
• Est. Priority Date: 11/12/2009
• Status: Active Grant

• Current Assignee: EM Microelectronic - Marin SA (The Swatch Group AG)
• Original Assignee: EM Microelectronic - Marin SA (The Swatch Group AG)
• Inventors: Kamp, David A., Marinelli, Filippo, Roz, Thierry
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US12/945,138
• Publication Number:
  US 20110115548A1
• Time in Patent Office: 886 Days
• Field of Search: 365/227, 365/228, 365/229, 365/226, 365/185.02, 365/185.04, 365/185.21, 365/185.23
• US Class Current: 365/185.04
• CPC Class Codes: E05B 2047/0058 by batteries
• CPC Class Codes: E05B 2047/0062 by generator
• CPC Class Codes: E05B 2047/0064 by solar cells
• CPC Class Codes: E05B 39/00 Locks giving indication of authorised or unauthorised unlocking with key identification means E05B35/001; alarm locks E05B45/00
• CPC Class Codes: E05B 45/06 Electric alarm locks E05B45/005 takes precedence
• CPC Class Codes: E05B 51/023 actuated in response to external pressure, blast or explosion E05B65/102 takes precedence
• CPC Class Codes: E05B 67/22 Padlocks with sliding shackles, with or without rotary or pivotal movement
• CPC Class Codes: G08B 13/06 by tampering with fastening
• CPC Class Codes: G08B 29/181 due to failing power supply

Abstract

The self-powered detection device comprises a non-volatile memory cell and a sensor activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester transforming energy from the physical or chemical action orphenomenon into an electrical stimulus pulse, the memory cell arranged for storing, by using electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon. The non-volatile memory cell comprises a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode, it receives on a set terminal a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.

Claims

1. A self-powered detection device comprising:

(a) at least a non-volatile memory cell; and

(b) a sensor activated by a physical or chemical action or phenomenon, wherein the sensor forms an energy harvester that transforms energy from the physical or chemical action or phenomenon into an electrical stimulus pulse, wherein the non-volatile memory cell is arranged for storing, by using the electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon applied to the sensor with at least a given strength or intensity, wherein the non-volatile memory cell comprises a first FET transistor having

i. a control gate;

ii. a first diffusion defining a first input; and

iii. a second diffusion defining a second input, and wherein the first FET transistor is set to a written logical state from an initial logical state when, in a detection mode of the self-powered detection device, the non-volatile memory cell receives on a set terminal, among the control gate and the first and second inputs, a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.

2. The self-powered detection device according to claim 1, wherein said set terminal is the control gate of the first FET transistor, and wherein said first input of the first FET transistor is connected to a ground potential of the sensor in said detection mode.

3. The self-powered detection device according to claim 2, wherein the first FET transistor is of a floating gate type with a tunnel oxide over a drain diffusion, and wherein said first input of the first FET transistor is the drain diffusion.

4. The self-powered detection device according to claim 3, wherein the self-powered detection device further comprises reset means or is arranged to be coupled to such reset means for resetting said non-volatile memory cell, wherein the reset means are, in a reset mode, arranged to reset the first FET transistor by applying a voltage signal of inversed polarity, relative to said voltage stimulus signal, between said control gate and said first input of the first FET transistor.

5. The self-powered detection device according to claim 4, wherein said reset means comprises a control circuit and a level shifter controlled by the control circuit.

6. The self-powered detection device according to claim 2, wherein the first FET transistor is of a floating gate type with a tunnel oxide over a channel zone or of a SONOS type, and wherein said first input of the first FET transistor is a drain of the first FET transistor or a source if the first FET transistor.

7. The self-powered detection device according to claim 6, wherein the self-powered detection device further comprises reset means or is arranged to be coupled to such reset means for resetting said non-volatile memory cell, wherein the reset means are, in a reset mode, arranged to reset the first FET transistor by applying a voltage signal of inversed polarity, relative to said voltage stimulus signal, between said control gate and said first input or said second input of the first FET transistor.

8. The self-powered detection device according to claim 7, wherein said reset means comprises a control circuit and a level shifter controlled by the control circuit.

9. The self-powered detection device according to claim 2, wherein the self-powered detection device further comprises reading means of the non-volatile memory cell or is arranged to be coupled to such reading means that are active when powered by a power source, wherein the reading means are, in a read mode, electrically connected to the first input or the second input of the first FET transistor and arranged to detect a state of the non-volatile memory cell by sensing a level of an electrical current flowing through the first input or the second input.

10. The self-powered detection device according to claim 9, wherein said reading means is formed by a latch providing at an output of the reading means a logical signal relative to the state of said first FET transistor.

11. The self-powered detection device according to claim 9, wherein an isolation circuit is provided between the first FET transistor and the reading means, wherein the isolation circuit is arranged for isolating the first FET transistor from the reading means in said detection mode and for connecting the first FET transistor to the reading means in said read mode.

12. The self-powered detection device according to claim 2, wherein the self-powered detection device further comprises a switch arranged between the ground potential of the sensor and said first input of the first FET transistor, and wherein the switch has a control gate connected to the control gate of the first FET transistor so that the first FET transistor is turned on when the voltage stimulus signal is provided to the control gate of the first FET transistor thereby connecting the first input of the first FET transistor to the ground potential.

13. The self-powered detection device according to claim 12, wherein said switch is formed by a second FET transistor having a control gate that is connected to said set terminal of said first FET transistor.

14. The self-powered detection device according to claim 1, wherein said set terminal is said first input of the first FET transistor, and wherein said control gate of the first FET transistor is connected to a ground potential of the sensor in said detection mode.

15. The self-powered detection device according to claim 14, wherein the first FET transistor is of a floating gate type with a tunnel oxide over a drain diffusion, and wherein said first input of the first FET transistor is the drain diffusion.

16. The self-powered detection device according to claim 15, wherein the self-powered detection device further comprises reset means or is arranged to be coupled to such reset means for resetting said non-volatile memory cell, wherein the reset means are, in a reset mode, arranged to reset the first FET transistor by applying a voltage signal of inversed polarity, relative to said voltage stimulus signal, between said control gate and said first input of the first FET transistor.

17. The self-powered detection device according to claim 5, wherein said reset means comprises a control circuit and a level shifter controlled by the control circuit.

18. The self-powered detection device according to claim 14, wherein the first FET transistor is of a floating gate type with a tunnel oxide over a channel zone or of a SONOS type, and wherein said first input of the first FET transistor is a drain of the first FET transistor or source of the first FET transistor.

19. The self-powered detection device according to claim 18, wherein the self-powered detection device further comprises reset means or is arranged to be coupled to such reset means for resetting said non-volatile memory cell, wherein the reset means are, in a reset mode, arranged to reset the first FET transistor by applying a voltage signal of inversed polarity, relative to said voltage stimulus signal, between said control gate and said first input or said second input of the first FET transistor.

20. The self-powered detection device according to claim 19, wherein said reset means comprises a control circuit and a level shifter controlled by the control circuit.

21. The self-powered detection device according to claim 14, wherein the self-powered detection device further comprises reading means of the non-volatile memory cell or is arranged to be coupled to such reading means that are active when powered by a power source, wherein the reading means are, in a read mode, electrically connected to the first input or the second input of the first FET transistor and arranged to detect a state of the non-volatile memory cell by sensing a level of an electrical current flowing through the first input or the second input.

22. The self-powered detection device according to claim 21, wherein said reading means is formed by a latch providing at an output of the reading means a logical signal relative to the state of said first FET transistor.

23. The self-powered detection device according to claim 21, wherein an isolation circuit is provided between the first FET transistor and the reading means, wherein the isolation circuit is arranged for isolating the first FET transistor from the reading means in said detection mode and for connecting the first FET transistor to the reading means in said read mode.

24. The self-powered detection device according to claim 14, wherein the self-powered detection device further comprises a switch arranged between the ground potential of the sensor and said control gate of the first FET transistor, and wherein the switch has a control gate connected to the set terminal of the first FET transistor so that the first FET transistor is turned on when the voltage stimulus signal is provided to the set terminal of the first FET transistor thereby connecting the control gate of the first FET transistor to the ground potential.

25. The self-powered detection device according to claim 24, wherein said switch is formed by a second FET transistor having a control gate that is connected to said set terminal of said first FET transistor.

26. The self-powered detection device according to claim 1, wherein the self-powered detection device further comprises reading means of the non-volatile memory cell or is arranged to be coupled to such reading means that are active when powered by a power source, wherein the reading means are, in a read mode, electrically connected to the first input or the second input of the first FET transistor and arranged to detect a state of the non-volatile memory cell by sensing a level of an electrical current flowing through the first input or the second input.

27. The self-powered detection device according to claim 26, wherein said reading means is formed by a latch providing at an output of the reading means a logical signal relative to the state of said first FET transistor.

28. The self-powered detection device according to claim 26, wherein an isolation circuit is provided between the first FET transistor and the reading means, wherein the isolation circuit is arranged for isolating the first FET transistor from the reading means in said detection mode and for connecting the first FET transistor to the reading means in said read mode.

29. The self-powered detection device according to claim 1, wherein said non-volatile memory cell is resetable, and wherein the self-powered detection device further comprises an OTP memory, wherein a bit of the OTP memory is automatically set when this OTP memory is powered and said non-volatile memory cell has been set to the written logical state.

30. The self-powered detection device according to claim 29, wherein said OTP memory comprises several bits that are successively set each time the non-volatile memory cell is set after a reset action.