Memory device and semiconductor device

• US 8,422,298 B2
• Filed: 03/10/2011
• Issued: 04/16/2013
• Est. Priority Date: 03/17/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko, Nagatsuka, Shuhei
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/044,656
• Publication Number:
  US 20110228602A1
• Time in Patent Office: 768 Days
• Field of Search: 365/189.2
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

One of objects is to provide a nonvolatile memory device in which the occurrence of a defect in data writing is suppressed and whose area can be suppressed, or a semiconductor device including the nonvolatile memory device. A first memory portion including a nonvolatile memory element and a second memory portion (data buffer) for temporarily storing data in verifying operation in which whether the data is correctly written into the first memory portion is verified are provided. Further, the second memory portion includes a memory element and an insulated gate field effect transistor for controlling the holding of charge in the memory element; the off-state current or the leakage current of the transistor is extremely low.

Claims

1. A semiconductor device comprising:

a first memory portion including a nonvolatile first memory element being capable of storing first data by writing of reference data;

a second memory portion including a first transistor and a second memory element being capable of storing second data by writing of the reference data; and

a comparison circuit configured to compare the first data with the second data,

wherein the first transistor includes an oxide semiconductor in a channel formation region, and

wherein one of a source and a drain of the first transistor is electrically connected to the second memory element.

2. The semiconductor device according to claim 1 further comprising a second transistor in the second memory element.

3. The semiconductor device according to claim 2, wherein the second transistor includes an oxide semiconductor in a channel formation region.

4. The semiconductor device according to claim 2, wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor.

5. The semiconductor device according to claim 1,

wherein the nonvolatile first memory element comprises a third transistor which includes a floating gate between a gate electrode and an active layer.

6. The semiconductor device according to claim 1,

wherein the oxide semiconductor comprises an In—

Ga—

Zn—

O-based oxide semiconductor.

7. The semiconductor device according to claim 1,

wherein hydrogen concentration of the channel formation region is lower than or equal to 5×

10¹⁹/cm³.

8. The semiconductor device according to claim 1,

wherein an off-state current density of the first transistor is lower than or equal to 100 zA/μ

m.

9. The semiconductor device according to claim 1, wherein the second memory element is capable of storing third data including a result of the comparison of the first data and the second data.

10. A semiconductor device comprising:

a first memory portion including a nonvolatile first memory element being capable of storing first data by writing of reference data;

a second memory portion including a first transistor and a second memory element being capable of storing second data by writing of the reference data; and

a comparison circuit configured to compare the first data with the second data,

wherein the first transistor includes an oxide semiconductor in a channel formation region,

wherein one of a source and a drain of the first transistor is electrically connected to the second memory element, and

wherein the second memory element includes a capacitor.

11. The semiconductor device according to claim 10 further comprising a second transistor in the second memory element.

12. The semiconductor device according to claim 11, wherein the second transistor includes an oxide semiconductor in a channel formation region.

13. The semiconductor device according to claim 11, wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor.

14. The semiconductor device according to claim 10,

wherein the nonvolatile first memory element comprises a third transistor which includes a floating gate between a gate electrode and an active layer.

15. The semiconductor device according to claim 10,

wherein the oxide semiconductor comprises an In—

Ga—

Zn—

O-based oxide semiconductor.

16. The semiconductor device according to claim 10,

wherein hydrogen concentration of the channel formation region is lower than or equal to 5×

10¹⁹/cm³.

17. The semiconductor device according to claim 10,

wherein an off-state current density of the first transistor is lower than or equal to 100 zA/μ

m.

18. The semiconductor device according to claim 10, wherein the second memory element is capable of storing third data including a result of the comparison of the first data and the second data.

19. A semiconductor device comprising:

a first memory portion including a nonvolatile first memory element being capable of storing first data by writing of reference data;

a second memory portion including a first transistor and a second memory element being capable of storing second data by writing of the reference data; and

a comparison circuit configured to compare the first data with the second data,

wherein the first transistor includes an oxide semiconductor in a channel formation region, and

wherein charge which is accumulated in the second memory element by writing of the reference data is held by the first transistor.

20. The semiconductor device according to claim 19 further comprising a second transistor in the second memory element.

21. The semiconductor device according to claim 20, wherein the second transistor includes an oxide semiconductor in a channel formation region.

22. The semiconductor device according to claim 20, wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor.

23. The semiconductor device according to claim 19,

wherein the nonvolatile first memory element comprises a third transistor which includes a floating gate between a gate electrode and an active layer.

24. The semiconductor device according to claim 19,

wherein the oxide semiconductor comprises an In—

Ga—

Zn—

O-based oxide semiconductor.

25. The semiconductor device according to claim 19,

wherein hydrogen concentration of the channel formation region is lower than or equal to 5×

10¹⁹/cm³.

26. The semiconductor device according to claim 19,

wherein an off-state current density of the first transistor is lower than or equal to 100 zA/μ

m.

27. The semiconductor device according to claim 19, wherein the second memory element is capable of storing third data including a result of the comparison of the first data and the second data.