Memory controller and memory controlling method

• US 8,422,330 B2
• Filed: 09/23/2011
• Issued: 04/16/2013
• Est. Priority Date: 12/24/2010
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited, Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Hatano, Hiroshi, Nishikawa, Takashi, Toichi, Masahiko
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US13/242,990
• Publication Number:
  US 20120163113A1
• Time in Patent Office: 571 Days
• Field of Search: 365/230.03, 365/230.06
• US Class Current: 365/230.03
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3455 using stride

Abstract

A memory controller includes: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory; a second generating unit that generates a position signal indicating a position of a data element to be selected from the data element sequence, and an order signal indicating a storing order for storing the data element to be selected into a register; and a selector unit that selects, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks, and stores the selected data element in the storing order indicated by the order signal into the register, wherein the data element stored in the register is processed in the storing order by a vector processor.

Claims

1. A memory controller comprising:

a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory, the memory having a plurality of the banks, from each of which the data element sequence is read out in response to an input of the read-address;

a second generating unit that generates a position signal indicating a position of a data element to be selected from the data element sequence, and an order signal indicating a storing order for storing the data element to be selected into a register; and

a selector unit that selects, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks, and stores the selected data element in the storing order indicated by the order signal into the register,

wherein the data element stored in the register is processed in the storing order by a vector processor.

2. The memory controller according to claim 1, wherein

the first generating unit further generates an enable signal indicating a validity of the read-address, and

the selector unit selects the data elements to be selected from the data element sequence read out from the bank for which the enable signal is generated, and does not select the data elements to be selected from the data element sequence read out from the bank for which the enable signal is not generated.

3. The memory controller according to claim 1, wherein

the order of the read-address of each of the plurality of the banks corresponds to the storing order of the data elements to be selected included within the data element sequence read out at the read-address, and

the second generating unit generates the order signal according to a first offset signal which is generated according to the read-address of each of the banks and indicates an order of the data element sequence read out from the plurality of the banks, and a second offset signal indicating an order of the data elements to be selected from each of the data element sequences read out from each of the plurality of the banks.

4. A memory controller comprising:

a first generating unit that generates a write-address to write a data element sequence having a plurality of data elements into a bank of a memory, the memory having a plurality of the banks, into each of which the data element sequence is written in response to an input of the write-address;

a second generating unit that generates an order signal indicating a storing order at the register of a data element to be written into the memory, the data elements begin stored in the register in a processing order of a vector processor, and generates a position signal indicating a position to insert the data element to be written into the data element sequence to be written into each of the plurality of the banks; and

a selector unit that inserts the data elements into the plurality of the banks indicated by the position signal in an order indicated by the order signal,

wherein the data element sequence including the data element to be written is written at the write-address of each of the banks.

5. The memory controller according to claim 4, wherein

the first generating unit further generates an enable signal indicating a validity of the write-address, and

the selector unit inserts the data element to be written into the data element sequence which is written into the bank for which the enable signal is generated, and does not insert the data element to be written into the data element sequence which is written into the bank for which the enable signal is not generated.

6. The memory controller according to claim 4, wherein

the selector unit inserts, according to a mask signal indicating enablement/disablement of writing of the data element, the data element enabled to be written into the data element sequence to be written into the plurality of the banks, and does not insert the data element disabled for writing into the data element sequence to be written into the plurality of the banks.

7. The memory controller according to claim 4, wherein

an order of the write-address of each of the banks corresponds to the storing order of the data element included within the data element sequence to be written into the write-address, and

the second generating unit generates a first offset signal indicating an order of the data element sequence written into the plurality of the banks, which is generated on the basis of the write-address of each of the banks, and a second offset signal indicating an order of the data elements to be written for each of the data element sequence to be written into each of the plurality of the banks.

8. A memory controlling method comprising:

generating a read-address to read a data element sequence having a plurality of data elements from a bank of a memory, the memory having a plurality of the banks, from each of which the data element sequence is read out in response to an input of the read-address;

generating a position signal indicating a position of the data element to be selected from the data element sequence;

generating an order signal indicating a storing order for storing the data elements to be selected into a register;

selecting, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks; and

storing the selected data element in a storing order indicated by the order signal into the register,

wherein the data element stored in the register is processed in the storing order by the vector processor.

9. A memory controlling method comprising:

generating a write-address to write a data element sequence having a plurality of data elements into a bank of a memory, the memory having a plurality of the banks, into each of which the data element sequence is written in response to an input of the write-address;

generating an order signal indicating a storing order at the register of the data elements to be written into the memory, the data elements begin stored in the register in a processing order of the vector processor;

generating a position signal indicating a position to insert the data elements into the data element sequence to be written into each of the plurality of the banks; and

inserting the data element into the plurality of the bank indicated by the position signal in an order indicated by the order signal,

wherein the data element sequence including the data element to be written is written at the write-address of each of the banks.