Method and system for an extended range ethernet line code

• US 8,422,512 B2
• Filed: 06/25/2010
• Issued: 04/16/2013
• Est. Priority Date: 09/20/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Yu, Xinhua, Chang, Kuang-Chou, Chen, Yencheng, Powell, Scott
• Primary Examiner(s): Nguyen, Brian D
• Application Number:
  US12/824,012
• Publication Number:
  US 20100260201A1
• Time in Patent Office: 1,026 Days
• Field of Search: 370/465, 341/51
• US Class Current: 370/465
• CPC Class Codes: H04L 12/40136 Nodes adapting their rate to the physical link properties LAN switches H04L49/351
• CPC Class Codes: H04L 25/4908 using mBnB codes
• CPC Class Codes: H04L 25/4923 using ternary codes H04L25/4927 takes precedence
• CPC Class Codes: H04L 5/1423 for simultaneous baseband signals

Abstract

Aspects of a method and system for an extended range Ethernet line code are provided. One or more ternary encoded bitstreams may be generated and transmitted. The generating may comprise mapping 3-bit binary IDLE patterns having a least significant bit of zero to a non-zero ternary value, and mapping 3-bit binary IDLE patterns having a non-zero least significant bit to a ternary zero. The generating may comprise receiving binary data via a media independent interface, mapping each 4-bit portion of said received binary data to a ternary symbol comprising two ternary bits, and transmitting said ternary symbol over said one or more physical channels. Data portions of the one or more ternary encoded bitstreams may be generated by mapping 3-bit binary patterns to 2-bit ternary symbols. One of the nine possible 2-bit ternary symbols may be reserved for control portions of said one or more ternary encoded bitstreams.

Claims

1. A method for communication, the method comprising:

generating one or more ternary encoded bitstreams, wherein said generating comprises mapping 3-bit binary IDLE patterns having a least significant bit of zero to a non-zero ternary value; and

transmitting said generated one or more ternary encoded bitstreams over one or more physical channels;

wherein said generating and said transmitting are performed by an Ethernet PHY that is configurable into at least two modes of operation, wherein;

while operating in a first mode of operation, said Ethernet PHY communicates in accordance with 10BASE-T, 100BASE-T, 1000BASE-T, or 10 GBASE-T standards; and

while operating in a second mode of operation, said Ethernet PHY performs said generating and said transmitting of said one or more ternary encoded bitstreams.

2. The method according to claim 1, wherein said generating comprises mapping 3-bit binary IDLE patterns having a non-zero least significant bit to a ternary zero.

3. The method according to claim 1, comprising:

multiplexing two of said ternary encoded bitstreams into a single ternary encoded bitstreams; and

transmitting said single ternary encoded bitstream over a single physical channel.

4. The method according to claim 1, wherein said generating of said ternary encoded bitstreams comprises:

receiving binary data via a media independent interface;

mapping each 4-bit portion of said received binary data to a ternary symbol comprising two ternary bits; and

transmitting said ternary symbol over said one or more physical channels.

5. A method for communication, the method comprising:

generating one or more ternary encoded bitstreams, wherein said generating comprises mapping 3-bit binary IDLE patterns having a non-zero least significant bit to a ternary zero; and

transmitting said generated one or more ternary encoded bitstreams over one or more physical channels;

wherein said generating and said transmitting are performed by an Ethernet PHY that is configurable into at least two modes of operation, wherein;

while operating in a first mode of operation, said Ethernet PHY communicates in accordance with 10BASE-T, 100BASE-T, 1000BASE-T, or 10GBASE-T standards; and

while operating in a second mode of operation, said Ethernet PHY performs said generating and said transmitting of said one or more ternary encoded bitstreams.

6. The method according to claim 5, wherein said generating comprises mapping 3-bit binary IDLE patterns having a least significant bit of zero to a non-zero ternary value.

7. The method according to claim 5, comprising:

multiplexing two of said ternary encoded bitstreams into a single ternary encoded bitstreams; and

transmitting said single ternary encoded bitstream over a single physical channel.

8. The method according to claim 5, wherein said generating of said ternary encoded bitstreams comprises:

receiving binary data via a media-independent interface;

mapping each 4-bit portion of said received binary data to a ternary symbol comprising two ternary bits; and

transmitting said ternary symbol over said one or more physical channels.

9. A method for communication, the method comprising:

generating one or more ternary encoded bitstreams; and

transmitting said one or more ternary encoded bitstreams over one or more physical channels, wherein;

data portions of said one or more ternary encoded bitstreams are generated by mapping 3-bit binary patterns to 2-bit ternary symbols; and

one of the nine possible 2-bit ternary symbols is reserved for control portions of said one or more ternary encoded bitstreams;

wherein said control portions of said ternary encoded bitstreams comprise a sequence of three of said 2-bit ternary symbols, and wherein each of a first two symbols of said sequence of three of said 2-bit ternary symbols comprises said symbol that is reserved, and a third symbol of said sequence indicates a control code being transmitted.

10. The method according to claim 9, wherein said control portions of said ternary encoded bitstreams comprise start of stream delimiters, end of stream delimiters, error indications, or any combination thereof.

11. A method for communication, the method comprising:

generating one or more ternary encoded bitstreams; and

transmitting said one or more ternary encoded bitstreams over one or more physical channels, wherein;

data portions of said one or more ternary encoded bitstreams are generated by mapping 3-bit binary patterns to 2-bit ternary symbols; and

one of the nine possible 2-bit ternary symbols is reserved for control portions of said one or more ternary encoded bitstreams;

wherein said generating and said transmitting are performed by an Ethernet PHY that is configurable into at least two modes of operation, wherein;

while operating in a first mode of operation, said Ethernet PHY communicates in accordance with 10BASE-T, 100BASE-T, 1000BASE-T, or 10GBASE-T standards; and

while operating in a second mode of operation, said Ethernet PHY performs said generating and said transmitting of said one or more ternary encoded bitstreams.

12. A system for communication, the system comprising:

one or more circuits and/or processors for use in an Ethernet PHY, said one or more circuits and/or processors being operable to;

generate one or more ternary encoded bitstreams, wherein said generation of said one or more ternary encoded bitstreams comprises mapping 3-bit binary IDLE patterns having a least significant bit of zero to a non-zero ternary value; and

transmit said generated one or more ternary encoded bitstreams over one or more physical channels;

wherein said Ethernet PHY is configurable into at least two modes of operation, wherein;

while operating in a first mode of operation, said one or more circuits and/or processors are operable to communicate in accordance with 10BASE-T, 100BASE-T, 1000BASE-T, or 10GBASE-T standards; and

while operating in a second mode of operation, said one or more circuits and/or processors are operable to perform said generation and said transmission of said one or more ternary encoded bitstreams.

13. The system according to claim 12, wherein said generation of said one or more ternary encoded bitstreams comprises mapping 3-bit binary IDLE patterns having a non-zero least significant bit to a ternary zero.

14. The system according to claim 12, wherein said one or more circuits and/or processors are operable to:

multiplex two of said ternary encoded bitstreams into a single ternary encoded bitstreams; and

transmit said single ternary encoded bitstream over a single physical channel.

15. The system according to claim 12, wherein said generation of said ternary encoded bitstreams comprises:

receiving binary data via a media independent interface;

mapping each 4-bit portion of said received binary data to a ternary symbol comprising two ternary bits; and

transmitting said ternary symbol over said one or more physical channels.

16. A system for communication, the system comprising:

one or more circuits and/or processors for use in an Ethernet PHY, said one or more circuits and/or processors being operable to;

generate one or more ternary encoded bitstreams, wherein said generation of said one or more ternary encoded bitstreams comprises mapping 3-bit binary IDLE patterns having a non-zero least significant bit to a ternary zero; and

transmit said generated one or more ternary encoded bitstreams over one or more physical channels;

wherein said Ethernet PHY is configurable into at least two modes of operation, wherein;

while operating in a first mode of operation, said one or more circuits and/or processors are operable to communicate in accordance with 10BASE-T, 100BASE-T, 1000BASE-T, or 10GBASE-T standards; and

while operating in a second mode of operation, said one or more circuits and/or processors are operable to perform said generation and said transmission of said one or more ternary encoded bitstreams.

17. The method according to claim 16, wherein said generation of said one or more ternary encoded bitstreams comprises mapping 3-bit binary IDLE patterns having a least significant bit of zero to a non-zero ternary value.

18. The system according to claim 16, wherein said one or more circuits and/or processors are operable to:

multiplex two of said ternary encoded bitstreams into a single ternary encoded bitstreams; and

transmit said single ternary encoded bitstream over a single physical channel.

19. The system according to claim 16, wherein said generation of said ternary encoded bitstreams comprises:

receiving binary data via a media independent interface;

mapping each 4-bit portion of said received binary data to a ternary symbol comprising two ternary bits; and

transmitting said ternary symbol over said one or more physical channels.

20. A system for communication, the system comprising:

one or more circuits and/or processors for use in an Ethernet PHY, said one or more circuits and/or processors being operable to;

generate one or more ternary encoded bitstreams; and

transmit said one or more ternary encoded bitstreams over one or more physical channels, wherein;

data portions of said one or more ternary encoded bitstreams are generated by mapping 3-bit binary patterns to 2-bit ternary symbols; and

one of the nine possible 2-bit ternary symbols is reserved for control portions of said one or more ternary encoded bitstreams;

wherein said control portions of said ternary encoded bitstreams comprise a sequence of three of said 2-bit ternary symbols, and wherein each of a first two symbols of said sequence of three of said 2-bit ternary symbols comprises said symbol that is reserved, and a third symbol of said sequence indicates control code being transmitted.

21. The system according to claim 20, wherein said control portions of said ternary encoded bitstreams comprise start of stream delimiters, end of stream delimiters, error indications, or any combination thereof.

22. A system for communication, the system comprising:

one or more circuits and/or processors for use in an Ethernet PHY, said one or more circuits and/or processors being operable to;

generate one or more ternary encoded bitstreams; and

transmit said one or more ternary encoded bitstreams over one or more physical channels, wherein;

data portions of said one or more ternary encoded bitstreams are generated by mapping 3-bit binary patterns to 2-bit ternary symbols; and

one of the nine possible 2-bit ternary symbols is reserved for control portions of said one or more ternary encoded bitstreams;

wherein said Ethernet PHY is configurable into at least two modes of operation, wherein;

while operating in a first mode of operation, said one or more circuits and/or processors are operable to communicate in accordance with 10BASE-T, 100BASE-T, 1000BASE-T, or 10GBASE-T standards; and

while operating in a second mode of operation, said one or more circuits and/or processors are operable to perform said generation and said transmission of said one or more ternary encoded bitstreams.