System and method of adjusting a resistance-based memory circuit parameter
First Claim
1. A method of determining a set of circuit parameters, the method comprising:
- determining a range of sizes for a clamp transistor and selecting a set of clamp transistors each having a size within the determined range of sizes;
for each clamp transistor in the set of clamp transistors;
executing a first simulation to generate a first contour graph representing current data over a range of statistical values, the first contour graph identifying a read disturbance area and a design range of a gate voltage of the clamp transistor and a load of the clamp transistor;
executing a second simulation to generate a second contour graph representing a sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor;
selecting a first sense margin based on the second contour graph and that satisfies the design range of the first contour graph; and
determining a second sense margin corresponding to a selected clamp transistor in the set of clamp transistors and selecting a corresponding gate voltage and a corresponding load of the selected clamp transistor based on the second sense margin.
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Accused Products
Abstract
Systems and methods of resistance-based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance-based memory circuit includes determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes. For each clamp transistor in the set of clamp transistors, a simulation may be executed to generate a first contour graph representing current values over a range of statistical values. The first contour graph may be used to identify a read disturbance area and a design range of the gate voltage of the clamp transistor and a load of the clamp transistor. The method may execute a simulation to generate a second contour graph representing sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor. A sense margin may be selected based on the second contour graph that also satisfies the design range of the first contour graph. A sense margin may be determined for a selected clamp transistor in the set of transistors and the corresponding gate voltage and the load of the selected clamp transistor is determined based on the determined sense margin.
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Citations
33 Claims
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1. A method of determining a set of circuit parameters, the method comprising:
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determining a range of sizes for a clamp transistor and selecting a set of clamp transistors each having a size within the determined range of sizes; for each clamp transistor in the set of clamp transistors; executing a first simulation to generate a first contour graph representing current data over a range of statistical values, the first contour graph identifying a read disturbance area and a design range of a gate voltage of the clamp transistor and a load of the clamp transistor; executing a second simulation to generate a second contour graph representing a sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor; selecting a first sense margin based on the second contour graph and that satisfies the design range of the first contour graph; and determining a second sense margin corresponding to a selected clamp transistor in the set of clamp transistors and selecting a corresponding gate voltage and a corresponding load of the selected clamp transistor based on the second sense margin. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of determining a set of circuit parameters, the method comprising:
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determining a range of sizes for a clamp transistor and selecting a set of clamp transistors each having a size within the determined range of sizes; for each clamp transistor in the set of clamp transistors; executing a first simulation to generate a first set of results representing current values over a first statistical range, the first set of results identifying a read disturbance range and a valid operating range of a gate voltage of the clamp transistor and a load of the clamp transistor; executing a second simulation to generate a second set of results representing a sense margin over a second statistical range and to identify values of the gate voltage of the clamp transistor and the load of the clamp transistor; selecting a particular sense margin above a sense margin threshold based on the second set of results and that satisfies the valid operating range of the first set of results; selecting a design sense margin of a sense amplifier, the design sense margin corresponding to a selected clamp transistor in the set of transistors based on the first set of results and based on the second set of results; and selecting a particular gate voltage of the selected clamp transistor and a size of a load transistor based on the selected design sense margin. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A sense amplifier circuit comprising:
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a p-type metal oxide semiconductor field effect (PMOS) transistor; and an n-type metal oxide semiconductor field effect (NMOS) transistor; wherein a size of the PMOS transistor and a gate voltage of the NMOS transistor are determined by; determining a range of sizes for the NMOS transistor and selecting a set of NMOS transistors having sizes within the determined range of sizes; for each transistor in the set of NMOS transistors; executing a first simulation to generate a first set of results representing current values over a first statistical range, the first set of results identifying a read disturbance range and a valid operating range of the gate voltage of the NMOS transistor and a load of the NMOS transistor; executing a second simulation to generate a second set of results representing a sense margin of a sense amplifier over a second statistical range and to identify values of the gate voltage of the NMOS transistor and the load of the NMOS transistor; selecting a particular sense margin of the sense amplifier that is above a sense margin threshold based on the second set of results and that is within the valid operating range of the first set of results; selecting a design sense margin for one transistor in the set of NMOS transistors based on the first set of results and based on the second set of results; and selecting the gate voltage of the NMOS transistor and the size of the PMOS transistor based on the selected design sense margin. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A processor readable medium having processor instructions that are executable to cause a processor to:
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determine a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes; for each clamp transistor in the set of clamp transistors; execute a first simulation to generate a first set of results representing current values over a first statistical range, the first set of results identifying a read disturbance range and a valid operating range of a gate voltage of the clamp transistor and a load of the clamp transistor; execute a second simulation to generate a second set of results representing a sense margin over a second statistical range and to identify values of the gate voltage of the clamp transistor and the load of the clamp transistor; select a particular sense margin above a sense margin threshold based on the second set of results and that satisfies the valid operating range of the first set of results; selecting a design sense margin of a sense amplifier, the design sense margin corresponding to a selected clamp transistor in the set of transistors based on the first set of results and based on the second set of results; and selecting the gate voltage of the selected clamp transistor and a size of a load transistor based on the selected design sense margin. - View Dependent Claims (24, 25)
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26. An apparatus comprising:
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means for determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes; for each clamp transistor in the set of clamp transistors; means for executing a first simulation to generate a first set of results representing current values over a first statistical range, the first set of results identifying a read disturbance range and a valid operating range of a gate voltage of the clamp transistor and a load of the clamp transistor; means for executing a second simulation to generate a second set of results representing a sense margin over a second statistical range and to identify values of the gate voltage of the clamp transistor and the load of the clamp transistor; means for selecting a particular sense margin above a sense margin threshold based on the second set of results and that satisfies the valid operating range of the first set of results; means for selecting a design sense margin of a sense amplifier, the design sense margin corresponding to a selected clamp transistor in the set of transistors based on the first set of results and based on the second set of results; and means for selecting a corresponding gate voltage of the selected clamp transistor and a size of a load transistor based on the selected design sense margin. - View Dependent Claims (27, 28)
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29. A method comprising:
receiving design information representing at least one physical property of a semiconductor device, the semiconductor device including; a load transistor; and a clamp transistor; wherein a size of the load transistor and a gate voltage of the clamp transistor are determined by; determining a range of sizes for the clamp transistor and selecting a set of clamp transistors having sizes within the range of sizes; for each transistor in the set of clamp transistors; executing a first simulation to generate a first set of results representing current values over a first statistical range, the first set of results identifying a read disturbance range and a valid operating range of the gate voltage of the clamp transistor and a load of the clamp transistor; executing a second simulation to generate a second set of results representing a sense margin of a sense amplifier over a second statistical range and to identify values of the gate voltage of the clamp transistor and the load of the clamp transistor; selecting a particular sense margin of the sense amplifier that is above a sense margin threshold based on the second set of results and that is within the valid operating range of the first set of results; selecting a design sense margin for one clamp transistor of the set of clamp transistors based on the first set of results and based on the second set of results; and selecting the gate voltage of the clamp transistor and the size of the load transistor based on the selected design sense margin; transforming the design information to comply with a file format; and generating a data file including the transformed design information. - View Dependent Claims (30)
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31. A method comprising:
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receiving a data file including design information including physical positioning information of a packaged semiconductor device on a circuit board; and manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises; a load transistor; and a clamp transistor; wherein a size of the load transistor and a gate voltage of the clamp transistor are determined by; determining a range of sizes for the clamp transistor and selecting a set of clamp transistors having sizes within the range of sizes; for each transistor in the set of clamp transistors; executing a first simulation to generate a first set of results representing current values over a first statistical range, the first set of results identifying a read disturbance range and a valid operating range of the gate voltage of the clamp transistor and a load of the clamp transistor; executing a second simulation to generate a second set of results representing a sense margin of a sense amplifier over a second statistical range and to identify values of the gate voltage of the clamp transistor and the load of the clamp transistor; selecting a particular sense margin of the sense amplifier that is above a sense margin threshold based on the second set of results and that is within the valid operating range of the first set of results; selecting a design sense margin for one clamp transistor of the set of clamp transistors based on the first set of results and based on the second set of results; and selecting the gate voltage of the clamp transistor and the size of the load transistor based on the selected design sense margin. - View Dependent Claims (32, 33)
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Specification