Non-volatile memory and method with post-write read and adaptive re-write to manage errors

• US 8,423,866 B2
• Filed: 12/18/2009
• Issued: 04/16/2013
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dusija, Gautam Ashok, Chen, Jian, Avila, Chris, Huang, Jianmin, Gavens, Lee M.
• Primary Examiner(s): MCCARTHY, CHRISTOPHER S
• Application Number:
  US12/642,728
• Publication Number:
  US 20110099460A1
• Time in Patent Office: 1,215 Days
• Field of Search: None
• US Class Current: 714/773
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.

Claims

1. A method of operating a non-volatile memory, comprising:

providing an error management for correcting errors liable to arise when the non-volatile memory ages through use;

providing a measure of the age of the non-volatile memory by the number of program/erase cycling undergone by the non-volatile memory;

commencing the error management only when the non-volatile memory has reached a predetermined age; and

said method further comprising;

configuring the memory into first and second portions, the first portion having memory cells operating with less error rate but lower density storage compared to the second portion;

programming input data into the first portion;

subsequently, copying the data to create a copy in the second portion; and

wherein the error correction management further comprises;

(a) checking the copy for error;

(b) identifying the copy as valid or invalid data depending on whether the error is less than a predetermined number of error bits or not;

(c) when the copy is identified as invalid, repeating the copying to another location in the second portion and steps (a) to (c) up to a predetermined number of times.

2. The method as in claim 1, wherein:

the non-volatile memory is organized into blocks of memory cells, each block of memory cells being erasable together;

said providing a measure of the age of the non-volatile memory is by tracking the number of program/erase cycling undergone by one of the blocks.

3. The method as in claim 2, wherein:

the predetermined age of the non-volatile memory is given by a predetermined number of program/erase cycling undergone by one of the blocks.

4. The method as in claim 1, wherein checking the copy for error is by an ECC associated with the copy.

5. The method as in claim 1, wherein

the memory is further organized into a plurality of erase blocks with memory cells in each block being erasable together;

and

the copying and checking are performed block by block.

6. The method as in claim 1, wherein:

the first portion has memory cells each storing 1 bit of data;

the second portion has memory cells each storing n bits of data, and

n>

1.

7. The method as in claim 1, wherein the error management further comprises:

identifying the data in the first portion corresponding to the copy in the second portion as valid when the copy is identified as invalid.

8. The method as in claim 1, wherein the error management further comprises:

identifying the data in the first portion corresponding to the copy in the second portion as invalid when the copy is identified as valid.

9. The method as in any one of claim 1-3 and 4-8, wherein the non-volatile memory is flash EEPROM.

10. A non-volatile memory, comprising:

an error management for correcting errors liable to arise when the non-volatile memory ages through use;

a measure of the age of the non-volatile memory by the number of program/erase cycling undergone by the non-volatile memory; and

wherein

said error management only commences after the non-volatile memory has reached a predetermined age; and

said non-volatile memory further comprising;

a memory controller; and

wherein;

the memory is configured into first and second portions, the first portion having memory cells operating with less error rate but lower density storage compared to the second portion;

the memory controller cooperating with the error correction management having operations including;

(a) programming input data into the first portion;

(b) subsequently, copying the data to create a copy in the second portion;

(c) checking the copy for error;

(d) identifying the copy as valid or invalid data depending on whether the error is less than a predetermined number of error bits or not; and

(e) when the copy is identified as invalid, repeating the copying to another location in the second portion and steps (c) to (e) up to a predetermined number of times.

11. The non-volatile memory as in claim 10, wherein:

the non-volatile memory is organized into blocks of memory cells, each block of memory cells being erasable together; and

said measure of the age of the non-volatile memory is given by the number of program/erase cycling undergone by one of the blocks.

12. The non-volatile memory as in claim 11, wherein:

the predetermined age of the non-volatile memory is given by a predetermined number of program/erase cycling undergone by one of the blocks.

13. The non-volatile memory as in claim 10, wherein the memory controller checking the copy for error is by an ECC associated with the copy.

14. The non-volatile memory as in claim 10, wherein:

the memory is further organized into a plurality of erase blocks with memory cells in each block being erasable together; and

the memory controller copying and checking are performed block by block.

15. The method as in claim 10, wherein:

the first portion has memory cells each storing 1 bit of data;

the second portion has memory cells each storing n bits of data, and

n>

1.

16. The non-volatile memory as in claim 10, wherein the error management further comprises:

identifying the data in the first portion corresponding to the copy in the second portion as valid when the copy is identified as invalid.

17. The non-volatile memory as in claim 10, wherein the error management further comprises:

identifying the data in the first portion corresponding to the copy in the second portion as invalid when the copy is identified as valid.

18. The non-volatile memory as in any one of claim 10-12 and 13-17, wherein the non-volatile memory is flash EEPROM.