System and method for compressed post-OPC data

• US 8,423,924 B1
• Filed: 12/19/2011
• Issued: 04/16/2013
• Est. Priority Date: 02/23/2009
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Pierrat, Christophe
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US13/330,566
• Time in Patent Office: 484 Days
• Field of Search: 716 50- 56, 430/5
• US Class Current: 716/53
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/68 Preparation processes not covered by groups G03F1/20 - G03F1/50
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Claims

1. A computer-aided design apparatus configured to generate photolithographic data for patterning a circuit design onto a semiconductor wafer, comprising:

a design tool having a processor, a memory connected to the processor, and a non-transitory computer readable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of;

receiving target layout data for the circuit design;

performing optical proximity correction on the target layout data to generate post-OPC layout data; and

calculating differences between the post-OPC layout data and the target layout data to generate post-OPC bias data; and

a manufacturing tool having a processor, a memory connected to the processor, and a non-transitory computer readable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of;

receiving the target layout data for the circuit design and the post-OPC bias data from the design tool; and

applying the post-OPC bias data to the target layout data to regenerate post-OPC layout data at the manufacturing tool.

2. The computer-aided design apparatus of claim 1, wherein calculating differences comprises:

determining a plurality of evaluation points for the target layout data, wherein the plurality of evaluation points corresponds to evaluation points used to perform optical proximity correction on a target layout; and

calculating a displacement between respective ones of the evaluation points for the target layout data and the evaluation points used to perform optical proximity correction.

3. The computer-aided design apparatus of claim 1, wherein the calculating differences is performed as part of performing optical proximity correction on the target layout data.

4. A method of generating photolithographic data for patterning a circuit design onto a semiconductor wafer, comprising:

receiving at a processor in a design tool target layout data for the circuit design;

performing optical proximity correction on the target layout data to generate post-OPC layout data at the design tool;

calculating differences between the post-OPC layout data and the target layout data to generate post-OPC bias data at the design tool;

receiving at a processor in a manufacturing tool the target layout data for the circuit design and the post-OPC bias data from the design tool; and

applying the post-OPC bias data to the target layout data to regenerate post-OPC layout data at the manufacturing tool.

5. The method of claim 4, wherein the calculating differences comprises:

determining a plurality of evaluation points for the target layout data, wherein the plurality of evaluation points corresponds to evaluation points used to perform optical proximity correction on a target layout; and

calculating a displacement between respective ones of the evaluation points for the target layout data and the evaluation points used to perform optical proximity correction.

6. The method of claim 4, wherein the calculating differences is performed as part of performing optical proximity correction on the target layout data.

7. A system to generate photolithographic data for patterning a circuit design onto a semiconductor wafer, comprising:

in a design tool, a first processor configured to receive target layout data for the circuit design, to perform optical proximity correction on the target layout data to generate post-OPC layout data, and to calculate differences between the post-OPC layout data and the target layout data to generate post-OPC bias data; and

in a manufacturing tool, a second processor configured to receive the target layout data for the circuit design and the post-OPC bias data from the first processor and to apply the post-OPC bias data to the target layout data to regenerate post-OPC layout data.

8. The system of claim 7, wherein the first processor calculates differences between the post-OPC layout data and the target layout data to generate post-OPC bias data by:

determining a plurality of evaluation points for the target layout data, wherein the plurality of evaluation points corresponds to evaluation points used to perform optical proximity correction on a target layout; and

calculating a displacement between respective ones of the evaluation points for the target layout data and the evaluation points used to perform optical proximity correction.

9. The system of claim 7, wherein the first processor calculates differences as part of performing optical proximity correction on the target layout data.