Method of forming a micro light emitting diode array

• US 8,426,227 B1
• Filed: 02/13/2012
• Issued: 04/23/2013
• Est. Priority Date: 11/18/2011
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Bibl, Andreas, Higginson, John A., Law, Hung-Fai Stephen, Hu, Hsin-Hua
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US13/372,245
• Time in Patent Office: 435 Days
• Field of Search: 438/42, 438/48, 438 52- 55, 438 21- 22, 438/27, 438/29, 438 46- 47, 438/455, 438/464, 257/95, 257/99, 257/79, 257/81, 257444-445
• US Class Current: 438/27
• CPC Class Codes: F21V 7/00 Reflectors for light sources characterised by cooling arrangements F21V29/505
• CPC Class Codes: H01L 2224/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/28 containing only elements of Group II and Group VI of the Periodic Table
• CPC Class Codes: H01L 33/30 containing only elements of Group III and Group V of the Periodic Table

Abstract

A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Claims

1. A method of forming a micro LED array comprising:

patterning a bonding layer on a carrier substrate to form a plurality of laterally separate locations of the bonding layer;

transferring a p-n diode layer and a metallization layer to the carrier substrate after patterning the bonding layer;

patterning the p-n diode layer to form a plurality of separate micro p-n diodes;

forming a conformal dielectric barrier layer spanning sidewalls of the plurality of separate micro p-n diodes.

2. The method of claim 1, wherein the conformal dielectric barrier layer is thinner than the plurality of separate micro p-n diodes and the metallization layer.

3. The method of claim 2, further comprising forming the conformal dielectric barrier layer partially along a bottom surface of each separate micro p-n diode.

4. The method of claim 3, further comprising forming the conformal dielectric barrier layer by atomic layer deposition (ALD).

5. The method of claim 1, wherein transferring the p-n diode layer and the metallization layer to the carrier substrate comprises bonding the metallization layer to the bonding layer on the carrier substrate.

6. The method of claim 5, wherein the bonding layer has liquidus temperature below approximately 350°

C.

7. The method of claim 6, wherein the bonding layer comprises indium or tin.

8. The method of claim 6, wherein the bonding layer consists essentially of indium or tin.

9. The method of claim 1, wherein transferring the p-n diode layer and the metallization layer to the carrier substrate further comprises:

transferring a patterned metallization layer to the carrier substrate, wherein the patterned metallization layer includes a plurality of separate locations of the metallization layer on the p-n diode layer; and

transferring a second patterned bonding layer to the carrier substrate, wherein the second bonding layer is formed over the patterned metallization layer.

10. The method of claim 5, wherein transferring the p-n diode layer and the metallization layer to the carrier substrate comprises transferring a patterned metallization layer to the carrier substrate, wherein the patterned metallization layer includes a plurality of separate locations of the metallization layer on the p-n diode layer.

11. The method of claim 10, further comprising patterning the p-n diode layer to form a plurality of micro mesas in the p-n diode layer prior to transferring the p-n diode layer and the patterned metallization layer from the growth substrate to the carrier substrate.

12. The method of claim 10, further comprising forming a plurality of pillars on the carrier substrate prior to transferring the p-n diode layer and the patterned metallization layer to the carrier substrate.

13. The method of claim 12, further comprising forming the bonding layer over the plurality of pillars on the carrier substrate prior to transferring the p-n diode layer and the patterned metallization layer to the carrier substrate.

18. The method of claim 1, further comprising forming a plurality of pillars on the carrier substrate prior to transferring the p-n diode layer and the metallization layer from the growth substrate to the carrier substrate.

19. The method of claim 1, wherein patterning the bonding layer on the carrier substrate to form the plurality of laterally separate locations of the bonding layer comprises forming the bonding layer over the plurality of pillars on the carrier substrate.

20. The method of claim 1, wherein transferring the p-n diode layer and the metallization layer to the carrier substrate comprises bonding the metallization layer to a bonding layer on the carrier substrate, and removing a growth substrate from the p-n diode layer.

21. The method of claim 20, wherein removing the growth substrate comprises an excimer laser-based lift-off (LLO) technique.

22. The method of claim 20, wherein the p-n diode layer comprises gallium nitride (GaN) and the growth substrate comprises sapphire.

14. A method of forming a micro LED array comprising:

transferring a p-n diode layer and a metallization layer to a carrier substrate, wherein transferring comprises bonding the metallization layer to a bonding layer on the carrier substrate;

patterning the p-n diode layer to form a plurality of separate micro p-n diodes;

patterning the metallization layer to form a respective plurality of separate locations of the metallization layer after transferring the p-n diode layer and the metallization layer to the carrier substrate and after patterning the p-n diode layer to form the plurality of separate micro p-n diodes;

patterning the bonding layer on the carrier substrate to form a respective plurality of laterally separate locations of the bonding layer; and

forming a conformal dielectric barrier layer spanning sidewalls of the plurality of separate micro p-n diodes.

15. The method of claim 14, further comprising forming the conformal dielectric barrier layer spanning sidewalls of the plurality of separate micro p-n diodes, sidewalls of the plurality of separate metallization layers, and sidewalls of the plurality of laterally separate locations of bonding layer.

16. The method of claim 14, wherein patterning the metallization layer comprises etching until a maximum width for each of the plurality of separate locations of the metallization layer is less than a width of a bottom surface of each of the plurality of separate micro p-n diodes.

17. The method of claim 14, wherein patterning the bonding layer comprises etching until a maximum width for each of the plurality of laterally separate locations of the bonding layer is less than a width of a bottom surface of each of the plurality of separate micro p-n diodes.

23. A method of forming a micro LED array comprising:

transferring a p-n diode layer and a metallization layer from a growth substrate to a plurality of pillars on a carrier substrate;

patterning the p-n diode layer to form a plurality of separate micro p-n diodes; and

forming a conformal dielectric barrier layer spanning sidewalls of the plurality of separate micro p-n diodes.

24. The method of claim 23, wherein transferring the p-n diode layer and the metallization layer to the plurality of pillars on the carrier substrate comprises placing the p-n diode layer and the metallization layer on a plurality of separate locations of a bonding layer on the plurality of pillars.

25. The method of claim 23, wherein patterning the p-n diode layer to form the plurality of separate micro p-n diodes comprises thinning the p-n diode layer.

26. The method of claim 25, wherein thinning the p-n diode layer comprises thinning a p-n diode layer including a plurality of connected pre-patterned micro mesas.

27. The method of claim 23, wherein transferring the p-n diode layer and the metallization layer to the plurality of pillars on the carrier substrate comprises transferring a patterned p-n diode layer including a corresponding plurality of laterally separate locations of the metallization layer.

28. The method of claim 24, wherein the bonding layer is a continuous layer formed on the plurality of pillars and within trenches between the plurality of pillars.

29. The method of claim 24, wherein the bonding layer is a discontinuous layer formed on the plurality of pillars.

30. The method of claim 23, further comprising forming the conformal dielectric barrier layer partially along a bottom surface of each separate micro p-n diode.