Vented die and package

• US 8,426,246 B2
• Filed: 02/21/2012
• Issued: 04/23/2013
• Est. Priority Date: 06/07/2007
• Status: Active Grant

• Current Assignee: Utac Headquarters Pte. Ltd (UTAC Holdings Ltd.)
• Original Assignee: United Test and Assembly Center Limited (UTAC Holdings Ltd.)
• Inventors: Toh, Chin Hock, Liu, Hao, Kolan, Ravi Kanth
• Primary Examiner(s): AU, BAC H
• Application Number:
  US13/400,578
• Publication Number:
  US 20120149150A1
• Time in Patent Office: 427 Days
• Field of Search: 438107-110
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/812 Applying energy for connecting
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.

Claims

1. A method of chip packaging comprising:

providing a package substrate having a bonding region on one of a top or bottom surface;

attaching and bonding a die directly to the bonding region, wherein the die which is directly bonded to the bonding region comprises unfilled and filled vias through first and second major surfaces of the die, wherein an unfilled via serves as a vent to release pressure generated during assembly; and

forming a package cap encapsulating the die having the unfilled and filled vias.

2. The method of claim 1 further comprising attaching a die stack comprising a plurality of dies, wherein at least one of the dies of the die stack comprises at least one unfilled via through first and second major surfaces of the die to serve as a vent to release pressure generated during assembly.

3. The method of claim 2 wherein each die of the die stack comprises at least one unfilled via to form a ventilation network for the die stack.

4. The method of claim 2 comprises forming the die stack on top of a mother die, wherein the mother die includes an active die or a dummy interposer.

5. The method of claim 2 wherein the die stack includes a plurality of through vias, and comprising filling the vias with conductive materials to form via contacts.

6. The method of claim 2 wherein the die stack comprises dies of a same type.

7. The method of claim 2 wherein the die stack comprises at least one die which is of a different type than other dies of the die stack.

8. The method of claim 2 wherein a top die of the die stack comprises a flip chip.

9. The method of claim 1 wherein the filled via is filled with conductive material and the unfilled via is masked during filling of a via to form the filled via.

10. The method of claim 1 wherein the filled via is filled with conductive material and the unfilled via is formed after filling a via to form the filled via.

11. A method of chip packaging comprising:

providing a carrier having a bonding region on one of a top or bottom surface;

attaching a die stack comprising a plurality of dies to the bonding region, wherein each die of the die stack comprises at least one unfilled via through first and second major surfaces of the dies to serve as a vent to release pressure generated during assembly; and

filling the unfilled via of a top die of the die stack with insulating material.

12. The method of claim 11 wherein the die stack further comprises a plurality of through vias, and comprising filling the vias with conductive materials to form via contacts.

13. A method of forming a semiconductor package comprising:

providing a plurality of dies, each of the dies having first and second major surfaces, wherein the dies are singulated dies of a wafer having a plurality of dies;

forming a plurality of through vias within the die, the plurality of vias include conductive materials to form via contacts;

forming at least one unfilled through via within each of the dies, the unfilled through via passing through the major surfaces of the dies;

stacking the plurality of dies having the via contacts and the at least one unfilled through via within each die to form a die stack;

attaching and bonding the die stack to a package substrate, wherein the unfilled through vias of the die stack which is bonded to the package substrate allow passage of air between the major surfaces of the dies to serve as a vent to release pressure generated during assembly; and

forming a package cap encapsulating the die stack having the via contacts and the unfilled through vias.

14. The method of claim 13 further comprises providing die contacts which are only coupled to the via contacts on the first or second major surface.

15. The method of claim 14 comprises:

reflowing the die contacts, wherein the unfilled through via within each die remains unfilled during the reflowing process and forming the package cap.

16. The method of claim 14 comprises:

providing underfill material between cavity of the first and second dies, wherein the unfilled through via within a top die of the die stack remains unfilled during providing the underfill material.

17. The method of claim 13 wherein forming the at least one unfilled through via is performed after forming the via contacts.

18. A method of forming a semiconductor package comprising:

providing a package substrate having a bonding region on one of a top or bottom surface;

attaching a die stack comprising at least a first die and a second die on top of the first die on the package substrate, wherein the first die is directly bonded to the bonding region of the package substrate and the first die comprises unfilled and filled through vias through first and major surfaces of the first die, wherein an unfilled through via allows passage of air between the major surfaces of the die to serve as a vent to release pressure generated during assembly; and

forming a package cap encapsulating the die stack having the unfilled and filled through vias in the first die.

19. The method of claim 18 wherein the second die comprises at least one unfilled through via.

20. The method of claim 19 wherein the die stack comprises three or more dies, wherein at least one of the three or more dies comprises at least one unfilled through via.

21. The method of claim 19 wherein the die stack comprises at least one die which is of a different type than other dies of the die stack.