Array substrate and method for manufacturing the same

• US 8,426,259 B2
• Filed: 06/01/2011
• Issued: 04/23/2013
• Est. Priority Date: 06/03/2010
• Status: Expired due to Fees

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Liu, Xiang, Yoo, Seongyeol, Xue, Jianshe
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US13/150,389
• Publication Number:
  US 20110297929A1
• Time in Patent Office: 692 Days
• Field of Search: 438/34, 438/149, 438/151, 438/158, 349/43, 349/106, 349/114, 257/43, 257/59, 257/72, 257/E29.101, 257/E33.012, 257/E33.037, 257/E33.062, 257/E33.064
• US Class Current: 438/158
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

The present invention provides an array substrate, comprising: a base substrate; a pixel electrode pattern and a gate pattern formed on the base substrate, the gate pattern comprises a gate scanning line and a gate electrode of a transistor, both of the gate scanning line and the gate electrode comprise transparent conductive metal layer and the gate metal layer stacking on the substrate, each pixel electrode in the pixel electrode pattern comprises transparent conductive metal layer; a gate insulating layer on the pixel electrode pattern and the gate pattern, an active layer pattern on the gate insulating layer and corresponding to the gate electrode, a via hole in the gate insulating layer for exposing the pixel electrode; and a source/drain pattern on the gate insulating layer, the source/drain pattern comprises a data scanning line crossing with the gate scanning line, source and drain electrodes of the transistor, and the drain electrode is in contact with the pixel electrode through the via hole.

Claims

1. A method for forming an array substrate comprising:

1) sequentially depositing a transparent conductive metal layer and a gate metal layer on a base substrate;

2) performing a patterning process by using a first dual-tone mask plate to form a pixel electrode pattern and a gate pattern comprising a gate electrode and a gate scanning line;

3) sequentially depositing a gate insulating layer and an active layer on the base substrate with the formed pixel electrode pattern and the gate pattern;

4) performing a patterning process by using a second dual-tone mask plate to form an active pattern corresponding to the gate electrode and a via hole in the gate insulating layer for exposing the pixel electrode, and remaining photoresist the active layer pattern;

5) depositing a source/drain metal layer on the base substrate with the active pattern and the via hole, through which the source/drain metal layer is in contact with the pixel electrode;

6) lifting off the photoresist remaining on the active layer pattern to remove the photoresist and a portion of the source/drain metal layer corresponding to the photoresist; and

7) performing a patterning process by using a third mask plate to forming a source/drain pattern, wherein the source/drain pattern comprises a data scanning line crossing with the gate scanning line, a source electrode and a drain electrode, and a portion of the drain electrode is in contact with the pixel electrode through the via hole.

2. The method of claim 1, wherein the step 2) comprises the following steps in sequence:

performing an exposing process by using the first dual-tone mask plate, so that a portion of the base substrate corresponding to the pixel electrode pattern is a partial-exposure region, a portion corresponding to the gate pattern is a non-exposure region, and the remaining portion is in a full-exposure region;

etching the transparent conductive metal layer and the gate metal layer in the full-exposure region by an etching process;

removing photoresist in the partial-exposure region by an ashing process, and etching thus exposed gate metal layer in the partial-exposure region by another etching process to expose the pixel electrode pattern, wherein a pixel electrode in the pixel electrode pattern comprises the transparent conductive metal layer; and

removing the photoresist in the non-exposure region to form the gate pattern, wherein both of the gate electrode and the gate scanning line in the gate pattern comprises the staked transparent conductive metal layer and gate metal layer.

3. The method of claim 1, wherein the step 4) comprises the following steps in sequence:

performing an exposing process by using the second dual-tone mask plate, so that a portion of the base substrate corresponding to the via hole is a full-exposure region, a portion corresponding to the active layer pattern is a non-exposure region, and the remaining portion is in a partial-exposure region;

etching the active layer and the gate insulating layer in the full-exposure region by an etching process, wherein the via hole penetrates through the gate insulating layer and exposes the underlying pixel electrode; and

removing photoresist in the partial-exposure region by an ashing process, and etching thus exposed active layer in the partial-exposure region by the etching process to form the active pattern corresponding to the gate electrode, wherein photoresist is remained on the active layer pattern.

4. The method of claim 1, wherein the step 7) comprises the following steps in sequence:

depositing a passivation layer on the base substrate, on which photoresist over the active layer pattern and the portion of the source/drain metal layer corresponding to the photoresist have been lifted off;

performing a patterning process by using the third mask plate to form the source/drain pattern and a passivation pattern, wherein the passivation pattern corresponds to the source/drain pattern and the active pattern.

5. The method of claim 1, wherein the active layer comprises an oxide semiconductor.

6. The method of claim 5, wherein the oxide semiconductor comprises amorphous indium gallium zinc oxide.